1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #ifndef __ASM_ARC_SMP_H
7*4882a593Smuzhiyun #define __ASM_ARC_SMP_H
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #ifdef CONFIG_SMP
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/types.h>
12*4882a593Smuzhiyun #include <linux/init.h>
13*4882a593Smuzhiyun #include <linux/threads.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #define raw_smp_processor_id() (current_thread_info()->cpu)
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun /* including cpumask.h leads to cyclic deps hence this Forward declaration */
18*4882a593Smuzhiyun struct cpumask;
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun /*
21*4882a593Smuzhiyun * APIs provided by arch SMP code to generic code
22*4882a593Smuzhiyun */
23*4882a593Smuzhiyun extern void arch_send_call_function_single_ipi(int cpu);
24*4882a593Smuzhiyun extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun /*
27*4882a593Smuzhiyun * APIs provided by arch SMP code to rest of arch code
28*4882a593Smuzhiyun */
29*4882a593Smuzhiyun extern void __init smp_init_cpus(void);
30*4882a593Smuzhiyun extern void first_lines_of_secondary(void);
31*4882a593Smuzhiyun extern const char *arc_platform_smp_cpuinfo(void);
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun /*
34*4882a593Smuzhiyun * API expected BY platform smp code (FROM arch smp code)
35*4882a593Smuzhiyun *
36*4882a593Smuzhiyun * smp_ipi_irq_setup:
37*4882a593Smuzhiyun * Takes @cpu and @hwirq to which the arch-common ISR is hooked up
38*4882a593Smuzhiyun */
39*4882a593Smuzhiyun extern int smp_ipi_irq_setup(int cpu, irq_hw_number_t hwirq);
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun /*
42*4882a593Smuzhiyun * struct plat_smp_ops - SMP callbacks provided by platform to ARC SMP
43*4882a593Smuzhiyun *
44*4882a593Smuzhiyun * @info: SoC SMP specific info for /proc/cpuinfo etc
45*4882a593Smuzhiyun * @init_early_smp: A SMP specific h/w block can init itself
46*4882a593Smuzhiyun * Could be common across platforms so not covered by
47*4882a593Smuzhiyun * mach_desc->init_early()
48*4882a593Smuzhiyun * @init_per_cpu: Called for each core so SMP h/w block driver can do
49*4882a593Smuzhiyun * any needed setup per cpu (e.g. IPI request)
50*4882a593Smuzhiyun * @cpu_kick: For Master to kickstart a cpu (optionally at a PC)
51*4882a593Smuzhiyun * @ipi_send: To send IPI to a @cpu
52*4882a593Smuzhiyun * @ips_clear: To clear IPI received at @irq
53*4882a593Smuzhiyun */
54*4882a593Smuzhiyun struct plat_smp_ops {
55*4882a593Smuzhiyun const char *info;
56*4882a593Smuzhiyun void (*init_early_smp)(void);
57*4882a593Smuzhiyun void (*init_per_cpu)(int cpu);
58*4882a593Smuzhiyun void (*cpu_kick)(int cpu, unsigned long pc);
59*4882a593Smuzhiyun void (*ipi_send)(int cpu);
60*4882a593Smuzhiyun void (*ipi_clear)(int irq);
61*4882a593Smuzhiyun };
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun /* TBD: stop exporting it for direct population by platform */
64*4882a593Smuzhiyun extern struct plat_smp_ops plat_smp_ops;
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun #else /* CONFIG_SMP */
67*4882a593Smuzhiyun
smp_init_cpus(void)68*4882a593Smuzhiyun static inline void smp_init_cpus(void) {}
arc_platform_smp_cpuinfo(void)69*4882a593Smuzhiyun static inline const char *arc_platform_smp_cpuinfo(void)
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun return "";
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun #endif /* !CONFIG_SMP */
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun /*
77*4882a593Smuzhiyun * ARC700 doesn't support atomic Read-Modify-Write ops.
78*4882a593Smuzhiyun * Originally Interrupts had to be disabled around code to gaurantee atomicity.
79*4882a593Smuzhiyun * The LLOCK/SCOND insns allow writing interrupt-hassle-free based atomic ops
80*4882a593Smuzhiyun * based on retry-if-irq-in-atomic (with hardware assist).
81*4882a593Smuzhiyun * However despite these, we provide the IRQ disabling variant
82*4882a593Smuzhiyun *
83*4882a593Smuzhiyun * (1) These insn were introduced only in 4.10 release. So for older released
84*4882a593Smuzhiyun * support needed.
85*4882a593Smuzhiyun *
86*4882a593Smuzhiyun * (2) In a SMP setup, the LLOCK/SCOND atomicity across CPUs needs to be
87*4882a593Smuzhiyun * gaurantted by the platform (not something which core handles).
88*4882a593Smuzhiyun * Assuming a platform won't, SMP Linux needs to use spinlocks + local IRQ
89*4882a593Smuzhiyun * disabling for atomicity.
90*4882a593Smuzhiyun *
91*4882a593Smuzhiyun * However exported spinlock API is not usable due to cyclic hdr deps
92*4882a593Smuzhiyun * (even after system.h disintegration upstream)
93*4882a593Smuzhiyun * asm/bitops.h -> linux/spinlock.h -> linux/preempt.h
94*4882a593Smuzhiyun * -> linux/thread_info.h -> linux/bitops.h -> asm/bitops.h
95*4882a593Smuzhiyun *
96*4882a593Smuzhiyun * So the workaround is to use the lowest level arch spinlock API.
97*4882a593Smuzhiyun * The exported spinlock API is smart enough to be NOP for !CONFIG_SMP,
98*4882a593Smuzhiyun * but same is not true for ARCH backend, hence the need for 2 variants
99*4882a593Smuzhiyun */
100*4882a593Smuzhiyun #ifndef CONFIG_ARC_HAS_LLSC
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun #include <linux/irqflags.h>
103*4882a593Smuzhiyun #ifdef CONFIG_SMP
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun #include <asm/spinlock.h>
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun extern arch_spinlock_t smp_atomic_ops_lock;
108*4882a593Smuzhiyun extern arch_spinlock_t smp_bitops_lock;
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun #define atomic_ops_lock(flags) do { \
111*4882a593Smuzhiyun local_irq_save(flags); \
112*4882a593Smuzhiyun arch_spin_lock(&smp_atomic_ops_lock); \
113*4882a593Smuzhiyun } while (0)
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun #define atomic_ops_unlock(flags) do { \
116*4882a593Smuzhiyun arch_spin_unlock(&smp_atomic_ops_lock); \
117*4882a593Smuzhiyun local_irq_restore(flags); \
118*4882a593Smuzhiyun } while (0)
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun #define bitops_lock(flags) do { \
121*4882a593Smuzhiyun local_irq_save(flags); \
122*4882a593Smuzhiyun arch_spin_lock(&smp_bitops_lock); \
123*4882a593Smuzhiyun } while (0)
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun #define bitops_unlock(flags) do { \
126*4882a593Smuzhiyun arch_spin_unlock(&smp_bitops_lock); \
127*4882a593Smuzhiyun local_irq_restore(flags); \
128*4882a593Smuzhiyun } while (0)
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun #else /* !CONFIG_SMP */
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun #define atomic_ops_lock(flags) local_irq_save(flags)
133*4882a593Smuzhiyun #define atomic_ops_unlock(flags) local_irq_restore(flags)
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun #define bitops_lock(flags) local_irq_save(flags)
136*4882a593Smuzhiyun #define bitops_unlock(flags) local_irq_restore(flags)
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun #endif /* !CONFIG_SMP */
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun #endif /* !CONFIG_ARC_HAS_LLSC */
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun #endif
143