1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _ASM_ARC_MMU_H 7*4882a593Smuzhiyun #define _ASM_ARC_MMU_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 10*4882a593Smuzhiyun #include <linux/threads.h> /* NR_CPUS */ 11*4882a593Smuzhiyun #endif 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #if defined(CONFIG_ARC_MMU_V1) 14*4882a593Smuzhiyun #define CONFIG_ARC_MMU_VER 1 15*4882a593Smuzhiyun #elif defined(CONFIG_ARC_MMU_V2) 16*4882a593Smuzhiyun #define CONFIG_ARC_MMU_VER 2 17*4882a593Smuzhiyun #elif defined(CONFIG_ARC_MMU_V3) 18*4882a593Smuzhiyun #define CONFIG_ARC_MMU_VER 3 19*4882a593Smuzhiyun #elif defined(CONFIG_ARC_MMU_V4) 20*4882a593Smuzhiyun #define CONFIG_ARC_MMU_VER 4 21*4882a593Smuzhiyun #endif 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /* MMU Management regs */ 24*4882a593Smuzhiyun #define ARC_REG_MMU_BCR 0x06f 25*4882a593Smuzhiyun #if (CONFIG_ARC_MMU_VER < 4) 26*4882a593Smuzhiyun #define ARC_REG_TLBPD0 0x405 27*4882a593Smuzhiyun #define ARC_REG_TLBPD1 0x406 28*4882a593Smuzhiyun #define ARC_REG_TLBPD1HI 0 /* Dummy: allows code sharing with ARC700 */ 29*4882a593Smuzhiyun #define ARC_REG_TLBINDEX 0x407 30*4882a593Smuzhiyun #define ARC_REG_TLBCOMMAND 0x408 31*4882a593Smuzhiyun #define ARC_REG_PID 0x409 32*4882a593Smuzhiyun #define ARC_REG_SCRATCH_DATA0 0x418 33*4882a593Smuzhiyun #else 34*4882a593Smuzhiyun #define ARC_REG_TLBPD0 0x460 35*4882a593Smuzhiyun #define ARC_REG_TLBPD1 0x461 36*4882a593Smuzhiyun #define ARC_REG_TLBPD1HI 0x463 37*4882a593Smuzhiyun #define ARC_REG_TLBINDEX 0x464 38*4882a593Smuzhiyun #define ARC_REG_TLBCOMMAND 0x465 39*4882a593Smuzhiyun #define ARC_REG_PID 0x468 40*4882a593Smuzhiyun #define ARC_REG_SCRATCH_DATA0 0x46c 41*4882a593Smuzhiyun #endif 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #if defined(CONFIG_ISA_ARCV2) || !defined(CONFIG_SMP) 44*4882a593Smuzhiyun #define ARC_USE_SCRATCH_REG 45*4882a593Smuzhiyun #endif 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* Bits in MMU PID register */ 48*4882a593Smuzhiyun #define __TLB_ENABLE (1 << 31) 49*4882a593Smuzhiyun #define __PROG_ENABLE (1 << 30) 50*4882a593Smuzhiyun #define MMU_ENABLE (__TLB_ENABLE | __PROG_ENABLE) 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* Error code if probe fails */ 53*4882a593Smuzhiyun #define TLB_LKUP_ERR 0x80000000 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #if (CONFIG_ARC_MMU_VER < 4) 56*4882a593Smuzhiyun #define TLB_DUP_ERR (TLB_LKUP_ERR | 0x00000001) 57*4882a593Smuzhiyun #else 58*4882a593Smuzhiyun #define TLB_DUP_ERR (TLB_LKUP_ERR | 0x40000000) 59*4882a593Smuzhiyun #endif 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* TLB Commands */ 62*4882a593Smuzhiyun #define TLBWrite 0x1 63*4882a593Smuzhiyun #define TLBRead 0x2 64*4882a593Smuzhiyun #define TLBGetIndex 0x3 65*4882a593Smuzhiyun #define TLBProbe 0x4 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #if (CONFIG_ARC_MMU_VER >= 2) 68*4882a593Smuzhiyun #define TLBWriteNI 0x5 /* write JTLB without inv uTLBs */ 69*4882a593Smuzhiyun #define TLBIVUTLB 0x6 /* explicitly inv uTLBs */ 70*4882a593Smuzhiyun #else 71*4882a593Smuzhiyun #define TLBWriteNI TLBWrite /* Not present in hardware, fallback */ 72*4882a593Smuzhiyun #endif 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #if (CONFIG_ARC_MMU_VER >= 4) 75*4882a593Smuzhiyun #define TLBInsertEntry 0x7 76*4882a593Smuzhiyun #define TLBDeleteEntry 0x8 77*4882a593Smuzhiyun #endif 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun typedef struct { 82*4882a593Smuzhiyun unsigned long asid[NR_CPUS]; /* 8 bit MMU PID + Generation cycle */ 83*4882a593Smuzhiyun } mm_context_t; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun #ifdef CONFIG_ARC_DBG_TLB_PARANOIA 86*4882a593Smuzhiyun void tlb_paranoid_check(unsigned int mm_asid, unsigned long address); 87*4882a593Smuzhiyun #else 88*4882a593Smuzhiyun #define tlb_paranoid_check(a, b) 89*4882a593Smuzhiyun #endif 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun void arc_mmu_init(void); 92*4882a593Smuzhiyun extern char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len); 93*4882a593Smuzhiyun void read_decode_mmu_bcr(void); 94*4882a593Smuzhiyun is_pae40_enabled(void)95*4882a593Smuzhiyunstatic inline int is_pae40_enabled(void) 96*4882a593Smuzhiyun { 97*4882a593Smuzhiyun return IS_ENABLED(CONFIG_ARC_HAS_PAE40); 98*4882a593Smuzhiyun } 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun extern int pae40_exist_but_not_enab(void); 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun #endif /* !__ASSEMBLY__ */ 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun #endif 105