1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun #ifndef _ASM_ARC_JUMP_LABEL_H
3*4882a593Smuzhiyun #define _ASM_ARC_JUMP_LABEL_H
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun #ifndef __ASSEMBLY__
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <linux/stringify.h>
8*4882a593Smuzhiyun #include <linux/types.h>
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #define JUMP_LABEL_NOP_SIZE 4
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun /*
13*4882a593Smuzhiyun * NOTE about '.balign 4':
14*4882a593Smuzhiyun *
15*4882a593Smuzhiyun * To make atomic update of patched instruction available we need to guarantee
16*4882a593Smuzhiyun * that this instruction doesn't cross L1 cache line boundary.
17*4882a593Smuzhiyun *
18*4882a593Smuzhiyun * As of today we simply align instruction which can be patched by 4 byte using
19*4882a593Smuzhiyun * ".balign 4" directive. In that case patched instruction is aligned with one
20*4882a593Smuzhiyun * 16-bit NOP_S if this is required.
21*4882a593Smuzhiyun * However 'align by 4' directive is much stricter than it actually required.
22*4882a593Smuzhiyun * It's enough that our 32-bit instruction don't cross L1 cache line boundary /
23*4882a593Smuzhiyun * L1 I$ fetch block boundary which can be achieved by using
24*4882a593Smuzhiyun * ".bundle_align_mode" assembler directive. That will save us from adding
25*4882a593Smuzhiyun * useless NOP_S padding in most of the cases.
26*4882a593Smuzhiyun *
27*4882a593Smuzhiyun * TODO: switch to ".bundle_align_mode" directive using whin it will be
28*4882a593Smuzhiyun * supported by ARC toolchain.
29*4882a593Smuzhiyun */
30*4882a593Smuzhiyun
arch_static_branch(struct static_key * key,bool branch)31*4882a593Smuzhiyun static __always_inline bool arch_static_branch(struct static_key *key,
32*4882a593Smuzhiyun bool branch)
33*4882a593Smuzhiyun {
34*4882a593Smuzhiyun asm_volatile_goto(".balign "__stringify(JUMP_LABEL_NOP_SIZE)" \n"
35*4882a593Smuzhiyun "1: \n"
36*4882a593Smuzhiyun "nop \n"
37*4882a593Smuzhiyun ".pushsection __jump_table, \"aw\" \n"
38*4882a593Smuzhiyun ".word 1b, %l[l_yes], %c0 \n"
39*4882a593Smuzhiyun ".popsection \n"
40*4882a593Smuzhiyun : : "i" (&((char *)key)[branch]) : : l_yes);
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun return false;
43*4882a593Smuzhiyun l_yes:
44*4882a593Smuzhiyun return true;
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun
arch_static_branch_jump(struct static_key * key,bool branch)47*4882a593Smuzhiyun static __always_inline bool arch_static_branch_jump(struct static_key *key,
48*4882a593Smuzhiyun bool branch)
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun asm_volatile_goto(".balign "__stringify(JUMP_LABEL_NOP_SIZE)" \n"
51*4882a593Smuzhiyun "1: \n"
52*4882a593Smuzhiyun "b %l[l_yes] \n"
53*4882a593Smuzhiyun ".pushsection __jump_table, \"aw\" \n"
54*4882a593Smuzhiyun ".word 1b, %l[l_yes], %c0 \n"
55*4882a593Smuzhiyun ".popsection \n"
56*4882a593Smuzhiyun : : "i" (&((char *)key)[branch]) : : l_yes);
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun return false;
59*4882a593Smuzhiyun l_yes:
60*4882a593Smuzhiyun return true;
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun typedef u32 jump_label_t;
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun struct jump_entry {
66*4882a593Smuzhiyun jump_label_t code;
67*4882a593Smuzhiyun jump_label_t target;
68*4882a593Smuzhiyun jump_label_t key;
69*4882a593Smuzhiyun };
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun #endif /* __ASSEMBLY__ */
72*4882a593Smuzhiyun #endif
73