1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2020 Synopsys, Inc. (www.synopsys.com) 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun #ifndef __ASM_ARC_DSP_H 8*4882a593Smuzhiyun #define __ASM_ARC_DSP_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* 13*4882a593Smuzhiyun * DSP-related saved registers - need to be saved only when you are 14*4882a593Smuzhiyun * scheduled out. 15*4882a593Smuzhiyun * structure fields name must correspond to aux register defenitions for 16*4882a593Smuzhiyun * automatic offset calculation in DSP_AUX_SAVE_RESTORE macros 17*4882a593Smuzhiyun */ 18*4882a593Smuzhiyun struct dsp_callee_regs { 19*4882a593Smuzhiyun unsigned long ACC0_GLO, ACC0_GHI, DSP_BFLY0, DSP_FFT_CTRL; 20*4882a593Smuzhiyun #ifdef CONFIG_ARC_DSP_AGU_USERSPACE 21*4882a593Smuzhiyun unsigned long AGU_AP0, AGU_AP1, AGU_AP2, AGU_AP3; 22*4882a593Smuzhiyun unsigned long AGU_OS0, AGU_OS1; 23*4882a593Smuzhiyun unsigned long AGU_MOD0, AGU_MOD1, AGU_MOD2, AGU_MOD3; 24*4882a593Smuzhiyun #endif 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #endif /* !__ASSEMBLY__ */ 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #endif /* __ASM_ARC_DSP_H */ 30