1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Support for peripherals on the AXS10x mainboard (VDK version) 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com) 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun/ { 9*4882a593Smuzhiyun axs10x_mb_vdk { 10*4882a593Smuzhiyun compatible = "simple-bus"; 11*4882a593Smuzhiyun #address-cells = <1>; 12*4882a593Smuzhiyun #size-cells = <1>; 13*4882a593Smuzhiyun ranges = <0x00000000 0xe0000000 0x10000000>; 14*4882a593Smuzhiyun interrupt-parent = <&mb_intc>; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun clocks { 17*4882a593Smuzhiyun apbclk: apbclk { 18*4882a593Smuzhiyun compatible = "fixed-clock"; 19*4882a593Smuzhiyun clock-frequency = <50000000>; 20*4882a593Smuzhiyun #clock-cells = <0>; 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun mmcclk: mmcclk { 24*4882a593Smuzhiyun compatible = "fixed-clock"; 25*4882a593Smuzhiyun clock-frequency = <50000000>; 26*4882a593Smuzhiyun #clock-cells = <0>; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun pguclk: pguclk { 30*4882a593Smuzhiyun #clock-cells = <0>; 31*4882a593Smuzhiyun compatible = "fixed-clock"; 32*4882a593Smuzhiyun clock-frequency = <25175000>; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun ethernet@18000 { 37*4882a593Smuzhiyun #interrupt-cells = <1>; 38*4882a593Smuzhiyun compatible = "snps,dwmac"; 39*4882a593Smuzhiyun reg = < 0x18000 0x2000 >; 40*4882a593Smuzhiyun interrupts = < 4 >; 41*4882a593Smuzhiyun interrupt-names = "macirq"; 42*4882a593Smuzhiyun phy-mode = "rgmii"; 43*4882a593Smuzhiyun snps,phy-addr = < 0 >; // VDK model phy address is 0 44*4882a593Smuzhiyun snps,pbl = < 32 >; 45*4882a593Smuzhiyun clocks = <&apbclk>; 46*4882a593Smuzhiyun clock-names = "stmmaceth"; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun ehci@40000 { 50*4882a593Smuzhiyun compatible = "generic-ehci"; 51*4882a593Smuzhiyun reg = < 0x40000 0x100 >; 52*4882a593Smuzhiyun interrupts = < 8 >; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun uart@20000 { 56*4882a593Smuzhiyun compatible = "snps,dw-apb-uart"; 57*4882a593Smuzhiyun reg = <0x20000 0x100>; 58*4882a593Smuzhiyun clock-frequency = <2403200>; 59*4882a593Smuzhiyun interrupts = <17>; 60*4882a593Smuzhiyun baud = <115200>; 61*4882a593Smuzhiyun reg-shift = <2>; 62*4882a593Smuzhiyun reg-io-width = <4>; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun uart@21000 { 66*4882a593Smuzhiyun compatible = "snps,dw-apb-uart"; 67*4882a593Smuzhiyun reg = <0x21000 0x100>; 68*4882a593Smuzhiyun clock-frequency = <2403200>; 69*4882a593Smuzhiyun interrupts = <18>; 70*4882a593Smuzhiyun baud = <115200>; 71*4882a593Smuzhiyun reg-shift = <2>; 72*4882a593Smuzhiyun reg-io-width = <4>; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun uart@22000 { 76*4882a593Smuzhiyun compatible = "snps,dw-apb-uart"; 77*4882a593Smuzhiyun reg = <0x22000 0x100>; 78*4882a593Smuzhiyun clock-frequency = <2403200>; 79*4882a593Smuzhiyun interrupts = <19>; 80*4882a593Smuzhiyun baud = <115200>; 81*4882a593Smuzhiyun reg-shift = <2>; 82*4882a593Smuzhiyun reg-io-width = <4>; 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun/* PGU output directly sent to virtual LCD screen; hdmi controller not modelled */ 86*4882a593Smuzhiyun pgu@17000 { 87*4882a593Smuzhiyun compatible = "snps,arcpgu"; 88*4882a593Smuzhiyun reg = <0x17000 0x400>; 89*4882a593Smuzhiyun clocks = <&pguclk>; 90*4882a593Smuzhiyun clock-names = "pxlclk"; 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun/* VDK has additional ps2 keyboard/mouse interface integrated in LCD screen model */ 94*4882a593Smuzhiyun ps2: ps2@e0017400 { 95*4882a593Smuzhiyun compatible = "snps,arc_ps2"; 96*4882a593Smuzhiyun reg = <0x17400 0x14>; 97*4882a593Smuzhiyun interrupts = <5>; 98*4882a593Smuzhiyun interrupt-names = "arc_ps2_irq"; 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun mmc@15000 { 102*4882a593Smuzhiyun compatible = "snps,dw-mshc"; 103*4882a593Smuzhiyun reg = <0x15000 0x400>; 104*4882a593Smuzhiyun fifo-depth = <1024>; 105*4882a593Smuzhiyun card-detect-delay = <200>; 106*4882a593Smuzhiyun clocks = <&apbclk>, <&mmcclk>; 107*4882a593Smuzhiyun clock-names = "biu", "ciu"; 108*4882a593Smuzhiyun interrupts = <7>; 109*4882a593Smuzhiyun bus-width = <4>; 110*4882a593Smuzhiyun }; 111*4882a593Smuzhiyun }; 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun /* 114*4882a593Smuzhiyun * Embedded Vision subsystem UIO mappings; only relevant for EV VDK 115*4882a593Smuzhiyun * 116*4882a593Smuzhiyun * This node is intentionally put outside of MB above becase 117*4882a593Smuzhiyun * it maps areas outside of MB's 0xez-0xfz. 118*4882a593Smuzhiyun */ 119*4882a593Smuzhiyun uio_ev: uio@d0000000 { 120*4882a593Smuzhiyun compatible = "generic-uio"; 121*4882a593Smuzhiyun reg = <0xd0000000 0x2000 0xd1000000 0x2000 0x90000000 0x10000000 0xc0000000 0x10000000>; 122*4882a593Smuzhiyun reg-names = "ev_gsa", "ev_ctrl", "ev_shared_mem", "ev_code_mem"; 123*4882a593Smuzhiyun interrupt-parent = <&mb_intc>; 124*4882a593Smuzhiyun interrupts = <23>; 125*4882a593Smuzhiyun }; 126*4882a593Smuzhiyun}; 127