1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (C) 2013, 2014 Synopsys, Inc. (www.synopsys.com) 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/* 7*4882a593Smuzhiyun * Device tree for AXC003 CPU card: HS38x UP configuration (VDK version) 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/include/ "skeleton_hs.dtsi" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/ { 13*4882a593Smuzhiyun compatible = "snps,arc"; 14*4882a593Smuzhiyun #address-cells = <1>; 15*4882a593Smuzhiyun #size-cells = <1>; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun cpu_card { 18*4882a593Smuzhiyun compatible = "simple-bus"; 19*4882a593Smuzhiyun #address-cells = <1>; 20*4882a593Smuzhiyun #size-cells = <1>; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun ranges = <0x00000000 0xf0000000 0x10000000>; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun core_clk: core_clk { 25*4882a593Smuzhiyun #clock-cells = <0>; 26*4882a593Smuzhiyun compatible = "fixed-clock"; 27*4882a593Smuzhiyun clock-frequency = <50000000>; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun core_intc: archs-intc@cpu { 31*4882a593Smuzhiyun compatible = "snps,archs-intc"; 32*4882a593Smuzhiyun interrupt-controller; 33*4882a593Smuzhiyun #interrupt-cells = <1>; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun debug_uart: dw-apb-uart@5000 { 37*4882a593Smuzhiyun compatible = "snps,dw-apb-uart"; 38*4882a593Smuzhiyun reg = <0x5000 0x100>; 39*4882a593Smuzhiyun clock-frequency = <2403200>; 40*4882a593Smuzhiyun interrupt-parent = <&core_intc>; 41*4882a593Smuzhiyun interrupts = <19>; 42*4882a593Smuzhiyun baud = <115200>; 43*4882a593Smuzhiyun reg-shift = <2>; 44*4882a593Smuzhiyun reg-io-width = <4>; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun mb_intc: interrupt-controller@e0012000 { 50*4882a593Smuzhiyun #interrupt-cells = <1>; 51*4882a593Smuzhiyun compatible = "snps,dw-apb-ictl"; 52*4882a593Smuzhiyun reg = < 0xe0012000 0x200 >; 53*4882a593Smuzhiyun interrupt-controller; 54*4882a593Smuzhiyun interrupt-parent = <&core_intc>; 55*4882a593Smuzhiyun interrupts = < 18 >; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun memory { 59*4882a593Smuzhiyun #address-cells = <1>; 60*4882a593Smuzhiyun #size-cells = <1>; 61*4882a593Smuzhiyun ranges = <0x00000000 0x80000000 0x40000000>; 62*4882a593Smuzhiyun device_type = "memory"; 63*4882a593Smuzhiyun reg = <0x80000000 0x20000000>; /* 512MiB */ 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun}; 66