1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (C) 2012 Synopsys, Inc. (www.synopsys.com) 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/* 7*4882a593Smuzhiyun * Skeleton device tree; the bare minimum needed to boot; just include and 8*4882a593Smuzhiyun * add a compatible value. 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/ { 12*4882a593Smuzhiyun compatible = "snps,arc"; 13*4882a593Smuzhiyun #address-cells = <1>; 14*4882a593Smuzhiyun #size-cells = <1>; 15*4882a593Smuzhiyun chosen { }; 16*4882a593Smuzhiyun aliases { }; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun cpus { 19*4882a593Smuzhiyun #address-cells = <1>; 20*4882a593Smuzhiyun #size-cells = <0>; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun cpu@0 { 23*4882a593Smuzhiyun device_type = "cpu"; 24*4882a593Smuzhiyun compatible = "snps,arc770d"; 25*4882a593Smuzhiyun reg = <0>; 26*4882a593Smuzhiyun clocks = <&core_clk>; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* TIMER0 with interrupt for clockevent */ 31*4882a593Smuzhiyun timer0 { 32*4882a593Smuzhiyun compatible = "snps,arc-timer"; 33*4882a593Smuzhiyun interrupts = <3>; 34*4882a593Smuzhiyun interrupt-parent = <&core_intc>; 35*4882a593Smuzhiyun clocks = <&core_clk>; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* TIMER1 for free running clocksource */ 39*4882a593Smuzhiyun timer1 { 40*4882a593Smuzhiyun compatible = "snps,arc-timer"; 41*4882a593Smuzhiyun clocks = <&core_clk>; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun memory { 45*4882a593Smuzhiyun device_type = "memory"; 46*4882a593Smuzhiyun reg = <0x80000000 0x10000000>; /* 256M */ 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun}; 49