1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com) 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun/dts-v1/; 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/include/ "skeleton_hs_idu.dtsi" 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun/ { 10*4882a593Smuzhiyun model = "snps,nsimosci_hs-smp"; 11*4882a593Smuzhiyun compatible = "snps,nsimosci_hs"; 12*4882a593Smuzhiyun #address-cells = <1>; 13*4882a593Smuzhiyun #size-cells = <1>; 14*4882a593Smuzhiyun interrupt-parent = <&core_intc>; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun chosen { 17*4882a593Smuzhiyun /* this is for console on serial */ 18*4882a593Smuzhiyun bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 consoleblan=0 debug video=640x480-24 print-fatal-signals=1"; 19*4882a593Smuzhiyun }; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun aliases { 22*4882a593Smuzhiyun serial0 = &uart0; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun fpga { 26*4882a593Smuzhiyun compatible = "simple-bus"; 27*4882a593Smuzhiyun #address-cells = <1>; 28*4882a593Smuzhiyun #size-cells = <1>; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* child and parent address space 1:1 mapped */ 31*4882a593Smuzhiyun ranges; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun core_clk: core_clk { 34*4882a593Smuzhiyun #clock-cells = <0>; 35*4882a593Smuzhiyun compatible = "fixed-clock"; 36*4882a593Smuzhiyun clock-frequency = <5000000>; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun core_intc: core-interrupt-controller { 40*4882a593Smuzhiyun compatible = "snps,archs-intc"; 41*4882a593Smuzhiyun interrupt-controller; 42*4882a593Smuzhiyun #interrupt-cells = <1>; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun idu_intc: idu-interrupt-controller { 46*4882a593Smuzhiyun compatible = "snps,archs-idu-intc"; 47*4882a593Smuzhiyun interrupt-controller; 48*4882a593Smuzhiyun interrupt-parent = <&core_intc>; 49*4882a593Smuzhiyun #interrupt-cells = <1>; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun uart0: serial@f0000000 { 53*4882a593Smuzhiyun compatible = "ns8250"; 54*4882a593Smuzhiyun reg = <0xf0000000 0x2000>; 55*4882a593Smuzhiyun interrupt-parent = <&idu_intc>; 56*4882a593Smuzhiyun interrupts = <0>; 57*4882a593Smuzhiyun clock-frequency = <3686400>; 58*4882a593Smuzhiyun baud = <115200>; 59*4882a593Smuzhiyun reg-shift = <2>; 60*4882a593Smuzhiyun reg-io-width = <4>; 61*4882a593Smuzhiyun no-loopback-test = <1>; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun pguclk: pguclk { 65*4882a593Smuzhiyun #clock-cells = <0>; 66*4882a593Smuzhiyun compatible = "fixed-clock"; 67*4882a593Smuzhiyun clock-frequency = <25175000>; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun pgu@f9000000 { 71*4882a593Smuzhiyun compatible = "snps,arcpgu"; 72*4882a593Smuzhiyun reg = <0xf9000000 0x400>; 73*4882a593Smuzhiyun clocks = <&pguclk>; 74*4882a593Smuzhiyun clock-names = "pxlclk"; 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun ps2: ps2@f9001000 { 78*4882a593Smuzhiyun compatible = "snps,arc_ps2"; 79*4882a593Smuzhiyun reg = <0xf9000400 0x14>; 80*4882a593Smuzhiyun interrupts = <3>; 81*4882a593Smuzhiyun interrupt-parent = <&idu_intc>; 82*4882a593Smuzhiyun interrupt-names = "arc_ps2_irq"; 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun eth0: ethernet@f0003000 { 86*4882a593Smuzhiyun compatible = "ezchip,nps-mgt-enet"; 87*4882a593Smuzhiyun reg = <0xf0003000 0x44>; 88*4882a593Smuzhiyun interrupt-parent = <&idu_intc>; 89*4882a593Smuzhiyun interrupts = <1>; 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun arcpct0: pct { 93*4882a593Smuzhiyun compatible = "snps,archs-pct"; 94*4882a593Smuzhiyun #interrupt-cells = <1>; 95*4882a593Smuzhiyun interrupts = <20>; 96*4882a593Smuzhiyun }; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun}; 99