1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Definitions for use with the Alpha wrperfmon PAL call. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __ALPHA_WRPERFMON_H 7*4882a593Smuzhiyun #define __ALPHA_WRPERFMON_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* Following commands are implemented on all CPUs */ 10*4882a593Smuzhiyun #define PERFMON_CMD_DISABLE 0 11*4882a593Smuzhiyun #define PERFMON_CMD_ENABLE 1 12*4882a593Smuzhiyun #define PERFMON_CMD_DESIRED_EVENTS 2 13*4882a593Smuzhiyun #define PERFMON_CMD_LOGGING_OPTIONS 3 14*4882a593Smuzhiyun /* Following commands on EV5/EV56/PCA56 only */ 15*4882a593Smuzhiyun #define PERFMON_CMD_INT_FREQ 4 16*4882a593Smuzhiyun #define PERFMON_CMD_ENABLE_CLEAR 7 17*4882a593Smuzhiyun /* Following commands are on EV5 and better CPUs */ 18*4882a593Smuzhiyun #define PERFMON_CMD_READ 5 19*4882a593Smuzhiyun #define PERFMON_CMD_WRITE 6 20*4882a593Smuzhiyun /* Following command are on EV6 and better CPUs */ 21*4882a593Smuzhiyun #define PERFMON_CMD_ENABLE_WRITE 7 22*4882a593Smuzhiyun /* Following command are on EV67 and better CPUs */ 23*4882a593Smuzhiyun #define PERFMON_CMD_I_STAT 8 24*4882a593Smuzhiyun #define PERFMON_CMD_PMPC 9 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* EV5/EV56/PCA56 Counters */ 28*4882a593Smuzhiyun #define EV5_PCTR_0 (1UL<<0) 29*4882a593Smuzhiyun #define EV5_PCTR_1 (1UL<<1) 30*4882a593Smuzhiyun #define EV5_PCTR_2 (1UL<<2) 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define EV5_PCTR_0_COUNT_SHIFT 48 33*4882a593Smuzhiyun #define EV5_PCTR_1_COUNT_SHIFT 32 34*4882a593Smuzhiyun #define EV5_PCTR_2_COUNT_SHIFT 16 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define EV5_PCTR_0_COUNT_MASK 0xffffUL 37*4882a593Smuzhiyun #define EV5_PCTR_1_COUNT_MASK 0xffffUL 38*4882a593Smuzhiyun #define EV5_PCTR_2_COUNT_MASK 0x3fffUL 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* EV6 Counters */ 41*4882a593Smuzhiyun #define EV6_PCTR_0 (1UL<<0) 42*4882a593Smuzhiyun #define EV6_PCTR_1 (1UL<<1) 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define EV6_PCTR_0_COUNT_SHIFT 28 45*4882a593Smuzhiyun #define EV6_PCTR_1_COUNT_SHIFT 6 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define EV6_PCTR_0_COUNT_MASK 0xfffffUL 48*4882a593Smuzhiyun #define EV6_PCTR_1_COUNT_MASK 0xfffffUL 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* EV67 (and subsequent) counters */ 51*4882a593Smuzhiyun #define EV67_PCTR_0 (1UL<<0) 52*4882a593Smuzhiyun #define EV67_PCTR_1 (1UL<<1) 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define EV67_PCTR_0_COUNT_SHIFT 28 55*4882a593Smuzhiyun #define EV67_PCTR_1_COUNT_SHIFT 6 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #define EV67_PCTR_0_COUNT_MASK 0xfffffUL 58*4882a593Smuzhiyun #define EV67_PCTR_1_COUNT_MASK 0xfffffUL 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* 62*4882a593Smuzhiyun * The Alpha Architecure Handbook, vers. 4 (1998) appears to have a misprint 63*4882a593Smuzhiyun * in Table E-23 regarding the bits that set the event PCTR 1 counts. 64*4882a593Smuzhiyun * Hopefully what we have here is correct. 65*4882a593Smuzhiyun */ 66*4882a593Smuzhiyun #define EV6_PCTR_0_EVENT_MASK 0x10UL 67*4882a593Smuzhiyun #define EV6_PCTR_1_EVENT_MASK 0x0fUL 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /* EV6 Events */ 70*4882a593Smuzhiyun #define EV6_PCTR_0_CYCLES (0UL << 4) 71*4882a593Smuzhiyun #define EV6_PCTR_0_INSTRUCTIONS (1UL << 4) 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #define EV6_PCTR_1_CYCLES 0 74*4882a593Smuzhiyun #define EV6_PCTR_1_BRANCHES 1 75*4882a593Smuzhiyun #define EV6_PCTR_1_BRANCH_MISPREDICTS 2 76*4882a593Smuzhiyun #define EV6_PCTR_1_DTB_SINGLE_MISSES 3 77*4882a593Smuzhiyun #define EV6_PCTR_1_DTB_DOUBLE_MISSES 4 78*4882a593Smuzhiyun #define EV6_PCTR_1_ITB_MISSES 5 79*4882a593Smuzhiyun #define EV6_PCTR_1_UNALIGNED_TRAPS 6 80*4882a593Smuzhiyun #define EV6_PCTR_1_REPLY_TRAPS 7 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* From the Alpha Architecture Reference Manual, 4th edn., 2002 */ 83*4882a593Smuzhiyun #define EV67_PCTR_MODE_MASK 0x10UL 84*4882a593Smuzhiyun #define EV67_PCTR_EVENT_MASK 0x0CUL 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun #define EV67_PCTR_MODE_PROFILEME (1UL<<4) 87*4882a593Smuzhiyun #define EV67_PCTR_MODE_AGGREGATE (0UL<<4) 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun #define EV67_PCTR_INSTR_CYCLES (0UL<<2) 90*4882a593Smuzhiyun #define EV67_PCTR_CYCLES_UNDEF (1UL<<2) 91*4882a593Smuzhiyun #define EV67_PCTR_INSTR_BCACHEMISS (2UL<<2) 92*4882a593Smuzhiyun #define EV67_PCTR_CYCLES_MBOX (3UL<<2) 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun #endif 95