1*4882a593Smuzhiyun=========================================== 2*4882a593SmuzhiyunAtomic Operation Control (ATOMCTL) Register 3*4882a593Smuzhiyun=========================================== 4*4882a593Smuzhiyun 5*4882a593SmuzhiyunWe Have Atomic Operation Control (ATOMCTL) Register. 6*4882a593SmuzhiyunThis register determines the effect of using a S32C1I instruction 7*4882a593Smuzhiyunwith various combinations of: 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun 1. With and without an Coherent Cache Controller which 10*4882a593Smuzhiyun can do Atomic Transactions to the memory internally. 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun 2. With and without An Intelligent Memory Controller which 13*4882a593Smuzhiyun can do Atomic Transactions itself. 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunThe Core comes up with a default value of for the three types of cache ops:: 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun 0x28: (WB: Internal, WT: Internal, BY:Exception) 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunOn the FPGA Cards we typically simulate an Intelligent Memory controller 20*4882a593Smuzhiyunwhich can implement RCW transactions. For FPGA cards with an External 21*4882a593SmuzhiyunMemory controller we let it to the atomic operations internally while 22*4882a593Smuzhiyundoing a Cached (WB) transaction and use the Memory RCW for un-cached 23*4882a593Smuzhiyunoperations. 24*4882a593Smuzhiyun 25*4882a593SmuzhiyunFor systems without an coherent cache controller, non-MX, we always 26*4882a593Smuzhiyunuse the memory controllers RCW, thought non-MX controlers likely 27*4882a593Smuzhiyunsupport the Internal Operation. 28*4882a593Smuzhiyun 29*4882a593SmuzhiyunCUSTOMER-WARNING: 30*4882a593Smuzhiyun Virtually all customers buy their memory controllers from vendors that 31*4882a593Smuzhiyun don't support atomic RCW memory transactions and will likely want to 32*4882a593Smuzhiyun configure this register to not use RCW. 33*4882a593Smuzhiyun 34*4882a593SmuzhiyunDevelopers might find using RCW in Bypass mode convenient when testing 35*4882a593Smuzhiyunwith the cache being bypassed; for example studying cache alias problems. 36*4882a593Smuzhiyun 37*4882a593SmuzhiyunSee Section 4.3.12.4 of ISA; Bits:: 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun WB WT BY 40*4882a593Smuzhiyun 5 4 | 3 2 | 1 0 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun========= ================== ================== =============== 43*4882a593Smuzhiyun 2 Bit 44*4882a593Smuzhiyun Field 45*4882a593Smuzhiyun Values WB - Write Back WT - Write Thru BY - Bypass 46*4882a593Smuzhiyun========= ================== ================== =============== 47*4882a593Smuzhiyun 0 Exception Exception Exception 48*4882a593Smuzhiyun 1 RCW Transaction RCW Transaction RCW Transaction 49*4882a593Smuzhiyun 2 Internal Operation Internal Operation Reserved 50*4882a593Smuzhiyun 3 Reserved Reserved Reserved 51*4882a593Smuzhiyun========= ================== ================== =============== 52