1*4882a593Smuzhiyun.. SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun========================= 4*4882a593SmuzhiyunMPIC interrupt controller 5*4882a593Smuzhiyun========================= 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunDevice types supported: 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun - KVM_DEV_TYPE_FSL_MPIC_20 Freescale MPIC v2.0 10*4882a593Smuzhiyun - KVM_DEV_TYPE_FSL_MPIC_42 Freescale MPIC v4.2 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunOnly one MPIC instance, of any type, may be instantiated. The created 13*4882a593SmuzhiyunMPIC will act as the system interrupt controller, connecting to each 14*4882a593Smuzhiyunvcpu's interrupt inputs. 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunGroups: 17*4882a593Smuzhiyun KVM_DEV_MPIC_GRP_MISC 18*4882a593Smuzhiyun Attributes: 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun KVM_DEV_MPIC_BASE_ADDR (rw, 64-bit) 21*4882a593Smuzhiyun Base address of the 256 KiB MPIC register space. Must be 22*4882a593Smuzhiyun naturally aligned. A value of zero disables the mapping. 23*4882a593Smuzhiyun Reset value is zero. 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun KVM_DEV_MPIC_GRP_REGISTER (rw, 32-bit) 26*4882a593Smuzhiyun Access an MPIC register, as if the access were made from the guest. 27*4882a593Smuzhiyun "attr" is the byte offset into the MPIC register space. Accesses 28*4882a593Smuzhiyun must be 4-byte aligned. 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun MSIs may be signaled by using this attribute group to write 31*4882a593Smuzhiyun to the relevant MSIIR. 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun KVM_DEV_MPIC_GRP_IRQ_ACTIVE (rw, 32-bit) 34*4882a593Smuzhiyun IRQ input line for each standard openpic source. 0 is inactive and 1 35*4882a593Smuzhiyun is active, regardless of interrupt sense. 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun For edge-triggered interrupts: Writing 1 is considered an activating 38*4882a593Smuzhiyun edge, and writing 0 is ignored. Reading returns 1 if a previously 39*4882a593Smuzhiyun signaled edge has not been acknowledged, and 0 otherwise. 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun "attr" is the IRQ number. IRQ numbers for standard sources are the 42*4882a593Smuzhiyun byte offset of the relevant IVPR from EIVPR0, divided by 32. 43*4882a593Smuzhiyun 44*4882a593SmuzhiyunIRQ Routing: 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun The MPIC emulation supports IRQ routing. Only a single MPIC device can 47*4882a593Smuzhiyun be instantiated. Once that device has been created, it's available as 48*4882a593Smuzhiyun irqchip id 0. 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun This irqchip 0 has 256 interrupt pins, which expose the interrupts in 51*4882a593Smuzhiyun the main array of interrupt sources (a.k.a. "SRC" interrupts). 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun The numbering is the same as the MPIC device tree binding -- based on 54*4882a593Smuzhiyun the register offset from the beginning of the sources array, without 55*4882a593Smuzhiyun regard to any subdivisions in chip documentation such as "internal" 56*4882a593Smuzhiyun or "external" interrupts. 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun Access to non-SRC interrupts is not implemented through IRQ routing mechanisms. 59