1*4882a593Smuzhiyun.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun.. _image-process-controls: 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun******************************* 6*4882a593SmuzhiyunImage Process Control Reference 7*4882a593Smuzhiyun******************************* 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunThe Image Process control class is intended for low-level control of 10*4882a593Smuzhiyunimage processing functions. Unlike ``V4L2_CID_IMAGE_SOURCE_CLASS``, the 11*4882a593Smuzhiyuncontrols in this class affect processing the image, and do not control 12*4882a593Smuzhiyuncapturing of it. 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun.. _image-process-control-id: 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunImage Process Control IDs 18*4882a593Smuzhiyun========================= 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun``V4L2_CID_IMAGE_PROC_CLASS (class)`` 21*4882a593Smuzhiyun The IMAGE_PROC class descriptor. 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun``V4L2_CID_LINK_FREQ (integer menu)`` 24*4882a593Smuzhiyun Data bus frequency. Together with the media bus pixel code, bus type 25*4882a593Smuzhiyun (clock cycles per sample), the data bus frequency defines the pixel 26*4882a593Smuzhiyun rate (``V4L2_CID_PIXEL_RATE``) in the pixel array (or possibly 27*4882a593Smuzhiyun elsewhere, if the device is not an image sensor). The frame rate can 28*4882a593Smuzhiyun be calculated from the pixel clock, image width and height and 29*4882a593Smuzhiyun horizontal and vertical blanking. While the pixel rate control may 30*4882a593Smuzhiyun be defined elsewhere than in the subdev containing the pixel array, 31*4882a593Smuzhiyun the frame rate cannot be obtained from that information. This is 32*4882a593Smuzhiyun because only on the pixel array it can be assumed that the vertical 33*4882a593Smuzhiyun and horizontal blanking information is exact: no other blanking is 34*4882a593Smuzhiyun allowed in the pixel array. The selection of frame rate is performed 35*4882a593Smuzhiyun by selecting the desired horizontal and vertical blanking. The unit 36*4882a593Smuzhiyun of this control is Hz. 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun``V4L2_CID_PIXEL_RATE (64-bit integer)`` 39*4882a593Smuzhiyun Pixel rate in the source pads of the subdev. This control is 40*4882a593Smuzhiyun read-only and its unit is pixels / second. 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun``V4L2_CID_TEST_PATTERN (menu)`` 43*4882a593Smuzhiyun Some capture/display/sensor devices have the capability to generate 44*4882a593Smuzhiyun test pattern images. These hardware specific test patterns can be 45*4882a593Smuzhiyun used to test if a device is working properly. 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun``V4L2_CID_DEINTERLACING_MODE (menu)`` 48*4882a593Smuzhiyun The video deinterlacing mode (such as Bob, Weave, ...). The menu items are 49*4882a593Smuzhiyun driver specific and are documented in :ref:`uapi-v4l-drivers`. 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun``V4L2_CID_DIGITAL_GAIN (integer)`` 52*4882a593Smuzhiyun Digital gain is the value by which all colour components 53*4882a593Smuzhiyun are multiplied by. Typically the digital gain applied is the 54*4882a593Smuzhiyun control value divided by e.g. 0x100, meaning that to get no 55*4882a593Smuzhiyun digital gain the control value needs to be 0x100. The no-gain 56*4882a593Smuzhiyun configuration is also typically the default. 57