1*4882a593Smuzhiyun================================== 2*4882a593SmuzhiyunASoC Digital Audio Interface (DAI) 3*4882a593Smuzhiyun================================== 4*4882a593Smuzhiyun 5*4882a593SmuzhiyunASoC currently supports the three main Digital Audio Interfaces (DAI) found on 6*4882a593SmuzhiyunSoC controllers and portable audio CODECs today, namely AC97, I2S and PCM. 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunAC97 10*4882a593Smuzhiyun==== 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunAC97 is a five wire interface commonly found on many PC sound cards. It is 13*4882a593Smuzhiyunnow also popular in many portable devices. This DAI has a reset line and time 14*4882a593Smuzhiyunmultiplexes its data on its SDATA_OUT (playback) and SDATA_IN (capture) lines. 15*4882a593SmuzhiyunThe bit clock (BCLK) is always driven by the CODEC (usually 12.288MHz) and the 16*4882a593Smuzhiyunframe (FRAME) (usually 48kHz) is always driven by the controller. Each AC97 17*4882a593Smuzhiyunframe is 21uS long and is divided into 13 time slots. 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunThe AC97 specification can be found at : 20*4882a593Smuzhiyunhttps://www.intel.com/p/en_US/business/design 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun 23*4882a593SmuzhiyunI2S 24*4882a593Smuzhiyun=== 25*4882a593Smuzhiyun 26*4882a593SmuzhiyunI2S is a common 4 wire DAI used in HiFi, STB and portable devices. The Tx and 27*4882a593SmuzhiyunRx lines are used for audio transmission, while the bit clock (BCLK) and 28*4882a593Smuzhiyunleft/right clock (LRC) synchronise the link. I2S is flexible in that either the 29*4882a593Smuzhiyuncontroller or CODEC can drive (master) the BCLK and LRC clock lines. Bit clock 30*4882a593Smuzhiyunusually varies depending on the sample rate and the master system clock 31*4882a593Smuzhiyun(SYSCLK). LRCLK is the same as the sample rate. A few devices support separate 32*4882a593SmuzhiyunADC and DAC LRCLKs, this allows for simultaneous capture and playback at 33*4882a593Smuzhiyundifferent sample rates. 34*4882a593Smuzhiyun 35*4882a593SmuzhiyunI2S has several different operating modes:- 36*4882a593Smuzhiyun 37*4882a593SmuzhiyunI2S 38*4882a593Smuzhiyun MSB is transmitted on the falling edge of the first BCLK after LRC 39*4882a593Smuzhiyun transition. 40*4882a593Smuzhiyun 41*4882a593SmuzhiyunLeft Justified 42*4882a593Smuzhiyun MSB is transmitted on transition of LRC. 43*4882a593Smuzhiyun 44*4882a593SmuzhiyunRight Justified 45*4882a593Smuzhiyun MSB is transmitted sample size BCLKs before LRC transition. 46*4882a593Smuzhiyun 47*4882a593SmuzhiyunPCM 48*4882a593Smuzhiyun=== 49*4882a593Smuzhiyun 50*4882a593SmuzhiyunPCM is another 4 wire interface, very similar to I2S, which can support a more 51*4882a593Smuzhiyunflexible protocol. It has bit clock (BCLK) and sync (SYNC) lines that are used 52*4882a593Smuzhiyunto synchronise the link while the Tx and Rx lines are used to transmit and 53*4882a593Smuzhiyunreceive the audio data. Bit clock usually varies depending on sample rate 54*4882a593Smuzhiyunwhile sync runs at the sample rate. PCM also supports Time Division 55*4882a593SmuzhiyunMultiplexing (TDM) in that several devices can use the bus simultaneously (this 56*4882a593Smuzhiyunis sometimes referred to as network mode). 57*4882a593Smuzhiyun 58*4882a593SmuzhiyunCommon PCM operating modes:- 59*4882a593Smuzhiyun 60*4882a593SmuzhiyunMode A 61*4882a593Smuzhiyun MSB is transmitted on falling edge of first BCLK after FRAME/SYNC. 62*4882a593Smuzhiyun 63*4882a593SmuzhiyunMode B 64*4882a593Smuzhiyun MSB is transmitted on rising edge of FRAME/SYNC. 65