1*4882a593Smuzhiyun==================================== 2*4882a593SmuzhiyunCoherent Accelerator Interface (CXL) 3*4882a593Smuzhiyun==================================== 4*4882a593Smuzhiyun 5*4882a593SmuzhiyunIntroduction 6*4882a593Smuzhiyun============ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun The coherent accelerator interface is designed to allow the 9*4882a593Smuzhiyun coherent connection of accelerators (FPGAs and other devices) to a 10*4882a593Smuzhiyun POWER system. These devices need to adhere to the Coherent 11*4882a593Smuzhiyun Accelerator Interface Architecture (CAIA). 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun IBM refers to this as the Coherent Accelerator Processor Interface 14*4882a593Smuzhiyun or CAPI. In the kernel it's referred to by the name CXL to avoid 15*4882a593Smuzhiyun confusion with the ISDN CAPI subsystem. 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun Coherent in this context means that the accelerator and CPUs can 18*4882a593Smuzhiyun both access system memory directly and with the same effective 19*4882a593Smuzhiyun addresses. 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunHardware overview 23*4882a593Smuzhiyun================= 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun :: 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun POWER8/9 FPGA 28*4882a593Smuzhiyun +----------+ +---------+ 29*4882a593Smuzhiyun | | | | 30*4882a593Smuzhiyun | CPU | | AFU | 31*4882a593Smuzhiyun | | | | 32*4882a593Smuzhiyun | | | | 33*4882a593Smuzhiyun | | | | 34*4882a593Smuzhiyun +----------+ +---------+ 35*4882a593Smuzhiyun | PHB | | | 36*4882a593Smuzhiyun | +------+ | PSL | 37*4882a593Smuzhiyun | | CAPP |<------>| | 38*4882a593Smuzhiyun +---+------+ PCIE +---------+ 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun The POWER8/9 chip has a Coherently Attached Processor Proxy (CAPP) 41*4882a593Smuzhiyun unit which is part of the PCIe Host Bridge (PHB). This is managed 42*4882a593Smuzhiyun by Linux by calls into OPAL. Linux doesn't directly program the 43*4882a593Smuzhiyun CAPP. 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun The FPGA (or coherently attached device) consists of two parts. 46*4882a593Smuzhiyun The POWER Service Layer (PSL) and the Accelerator Function Unit 47*4882a593Smuzhiyun (AFU). The AFU is used to implement specific functionality behind 48*4882a593Smuzhiyun the PSL. The PSL, among other things, provides memory address 49*4882a593Smuzhiyun translation services to allow each AFU direct access to userspace 50*4882a593Smuzhiyun memory. 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun The AFU is the core part of the accelerator (eg. the compression, 53*4882a593Smuzhiyun crypto etc function). The kernel has no knowledge of the function 54*4882a593Smuzhiyun of the AFU. Only userspace interacts directly with the AFU. 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun The PSL provides the translation and interrupt services that the 57*4882a593Smuzhiyun AFU needs. This is what the kernel interacts with. For example, if 58*4882a593Smuzhiyun the AFU needs to read a particular effective address, it sends 59*4882a593Smuzhiyun that address to the PSL, the PSL then translates it, fetches the 60*4882a593Smuzhiyun data from memory and returns it to the AFU. If the PSL has a 61*4882a593Smuzhiyun translation miss, it interrupts the kernel and the kernel services 62*4882a593Smuzhiyun the fault. The context to which this fault is serviced is based on 63*4882a593Smuzhiyun who owns that acceleration function. 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun - POWER8 and PSL Version 8 are compliant to the CAIA Version 1.0. 66*4882a593Smuzhiyun - POWER9 and PSL Version 9 are compliant to the CAIA Version 2.0. 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun This PSL Version 9 provides new features such as: 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun * Interaction with the nest MMU on the P9 chip. 71*4882a593Smuzhiyun * Native DMA support. 72*4882a593Smuzhiyun * Supports sending ASB_Notify messages for host thread wakeup. 73*4882a593Smuzhiyun * Supports Atomic operations. 74*4882a593Smuzhiyun * etc. 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun Cards with a PSL9 won't work on a POWER8 system and cards with a 77*4882a593Smuzhiyun PSL8 won't work on a POWER9 system. 78*4882a593Smuzhiyun 79*4882a593SmuzhiyunAFU Modes 80*4882a593Smuzhiyun========= 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun There are two programming modes supported by the AFU. Dedicated 83*4882a593Smuzhiyun and AFU directed. AFU may support one or both modes. 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun When using dedicated mode only one MMU context is supported. In 86*4882a593Smuzhiyun this mode, only one userspace process can use the accelerator at 87*4882a593Smuzhiyun time. 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun When using AFU directed mode, up to 16K simultaneous contexts can 90*4882a593Smuzhiyun be supported. This means up to 16K simultaneous userspace 91*4882a593Smuzhiyun applications may use the accelerator (although specific AFUs may 92*4882a593Smuzhiyun support fewer). In this mode, the AFU sends a 16 bit context ID 93*4882a593Smuzhiyun with each of its requests. This tells the PSL which context is 94*4882a593Smuzhiyun associated with each operation. If the PSL can't translate an 95*4882a593Smuzhiyun operation, the ID can also be accessed by the kernel so it can 96*4882a593Smuzhiyun determine the userspace context associated with an operation. 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun 99*4882a593SmuzhiyunMMIO space 100*4882a593Smuzhiyun========== 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun A portion of the accelerator MMIO space can be directly mapped 103*4882a593Smuzhiyun from the AFU to userspace. Either the whole space can be mapped or 104*4882a593Smuzhiyun just a per context portion. The hardware is self describing, hence 105*4882a593Smuzhiyun the kernel can determine the offset and size of the per context 106*4882a593Smuzhiyun portion. 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun 109*4882a593SmuzhiyunInterrupts 110*4882a593Smuzhiyun========== 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun AFUs may generate interrupts that are destined for userspace. These 113*4882a593Smuzhiyun are received by the kernel as hardware interrupts and passed onto 114*4882a593Smuzhiyun userspace by a read syscall documented below. 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun Data storage faults and error interrupts are handled by the kernel 117*4882a593Smuzhiyun driver. 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun 120*4882a593SmuzhiyunWork Element Descriptor (WED) 121*4882a593Smuzhiyun============================= 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun The WED is a 64-bit parameter passed to the AFU when a context is 124*4882a593Smuzhiyun started. Its format is up to the AFU hence the kernel has no 125*4882a593Smuzhiyun knowledge of what it represents. Typically it will be the 126*4882a593Smuzhiyun effective address of a work queue or status block where the AFU 127*4882a593Smuzhiyun and userspace can share control and status information. 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun 132*4882a593SmuzhiyunUser API 133*4882a593Smuzhiyun======== 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun1. AFU character devices 136*4882a593Smuzhiyun^^^^^^^^^^^^^^^^^^^^^^^^ 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun For AFUs operating in AFU directed mode, two character device 139*4882a593Smuzhiyun files will be created. /dev/cxl/afu0.0m will correspond to a 140*4882a593Smuzhiyun master context and /dev/cxl/afu0.0s will correspond to a slave 141*4882a593Smuzhiyun context. Master contexts have access to the full MMIO space an 142*4882a593Smuzhiyun AFU provides. Slave contexts have access to only the per process 143*4882a593Smuzhiyun MMIO space an AFU provides. 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun For AFUs operating in dedicated process mode, the driver will 146*4882a593Smuzhiyun only create a single character device per AFU called 147*4882a593Smuzhiyun /dev/cxl/afu0.0d. This will have access to the entire MMIO space 148*4882a593Smuzhiyun that the AFU provides (like master contexts in AFU directed). 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun The types described below are defined in include/uapi/misc/cxl.h 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun The following file operations are supported on both slave and 153*4882a593Smuzhiyun master devices. 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun A userspace library libcxl is available here: 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun https://github.com/ibm-capi/libcxl 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun This provides a C interface to this kernel API. 160*4882a593Smuzhiyun 161*4882a593Smuzhiyunopen 162*4882a593Smuzhiyun---- 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun Opens the device and allocates a file descriptor to be used with 165*4882a593Smuzhiyun the rest of the API. 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun A dedicated mode AFU only has one context and only allows the 168*4882a593Smuzhiyun device to be opened once. 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun An AFU directed mode AFU can have many contexts, the device can be 171*4882a593Smuzhiyun opened once for each context that is available. 172*4882a593Smuzhiyun 173*4882a593Smuzhiyun When all available contexts are allocated the open call will fail 174*4882a593Smuzhiyun and return -ENOSPC. 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun Note: 177*4882a593Smuzhiyun IRQs need to be allocated for each context, which may limit 178*4882a593Smuzhiyun the number of contexts that can be created, and therefore 179*4882a593Smuzhiyun how many times the device can be opened. The POWER8 CAPP 180*4882a593Smuzhiyun supports 2040 IRQs and 3 are used by the kernel, so 2037 are 181*4882a593Smuzhiyun left. If 1 IRQ is needed per context, then only 2037 182*4882a593Smuzhiyun contexts can be allocated. If 4 IRQs are needed per context, 183*4882a593Smuzhiyun then only 2037/4 = 509 contexts can be allocated. 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun 186*4882a593Smuzhiyunioctl 187*4882a593Smuzhiyun----- 188*4882a593Smuzhiyun 189*4882a593Smuzhiyun CXL_IOCTL_START_WORK: 190*4882a593Smuzhiyun Starts the AFU context and associates it with the current 191*4882a593Smuzhiyun process. Once this ioctl is successfully executed, all memory 192*4882a593Smuzhiyun mapped into this process is accessible to this AFU context 193*4882a593Smuzhiyun using the same effective addresses. No additional calls are 194*4882a593Smuzhiyun required to map/unmap memory. The AFU memory context will be 195*4882a593Smuzhiyun updated as userspace allocates and frees memory. This ioctl 196*4882a593Smuzhiyun returns once the AFU context is started. 197*4882a593Smuzhiyun 198*4882a593Smuzhiyun Takes a pointer to a struct cxl_ioctl_start_work 199*4882a593Smuzhiyun 200*4882a593Smuzhiyun :: 201*4882a593Smuzhiyun 202*4882a593Smuzhiyun struct cxl_ioctl_start_work { 203*4882a593Smuzhiyun __u64 flags; 204*4882a593Smuzhiyun __u64 work_element_descriptor; 205*4882a593Smuzhiyun __u64 amr; 206*4882a593Smuzhiyun __s16 num_interrupts; 207*4882a593Smuzhiyun __s16 reserved1; 208*4882a593Smuzhiyun __s32 reserved2; 209*4882a593Smuzhiyun __u64 reserved3; 210*4882a593Smuzhiyun __u64 reserved4; 211*4882a593Smuzhiyun __u64 reserved5; 212*4882a593Smuzhiyun __u64 reserved6; 213*4882a593Smuzhiyun }; 214*4882a593Smuzhiyun 215*4882a593Smuzhiyun flags: 216*4882a593Smuzhiyun Indicates which optional fields in the structure are 217*4882a593Smuzhiyun valid. 218*4882a593Smuzhiyun 219*4882a593Smuzhiyun work_element_descriptor: 220*4882a593Smuzhiyun The Work Element Descriptor (WED) is a 64-bit argument 221*4882a593Smuzhiyun defined by the AFU. Typically this is an effective 222*4882a593Smuzhiyun address pointing to an AFU specific structure 223*4882a593Smuzhiyun describing what work to perform. 224*4882a593Smuzhiyun 225*4882a593Smuzhiyun amr: 226*4882a593Smuzhiyun Authority Mask Register (AMR), same as the powerpc 227*4882a593Smuzhiyun AMR. This field is only used by the kernel when the 228*4882a593Smuzhiyun corresponding CXL_START_WORK_AMR value is specified in 229*4882a593Smuzhiyun flags. If not specified the kernel will use a default 230*4882a593Smuzhiyun value of 0. 231*4882a593Smuzhiyun 232*4882a593Smuzhiyun num_interrupts: 233*4882a593Smuzhiyun Number of userspace interrupts to request. This field 234*4882a593Smuzhiyun is only used by the kernel when the corresponding 235*4882a593Smuzhiyun CXL_START_WORK_NUM_IRQS value is specified in flags. 236*4882a593Smuzhiyun If not specified the minimum number required by the 237*4882a593Smuzhiyun AFU will be allocated. The min and max number can be 238*4882a593Smuzhiyun obtained from sysfs. 239*4882a593Smuzhiyun 240*4882a593Smuzhiyun reserved fields: 241*4882a593Smuzhiyun For ABI padding and future extensions 242*4882a593Smuzhiyun 243*4882a593Smuzhiyun CXL_IOCTL_GET_PROCESS_ELEMENT: 244*4882a593Smuzhiyun Get the current context id, also known as the process element. 245*4882a593Smuzhiyun The value is returned from the kernel as a __u32. 246*4882a593Smuzhiyun 247*4882a593Smuzhiyun 248*4882a593Smuzhiyunmmap 249*4882a593Smuzhiyun---- 250*4882a593Smuzhiyun 251*4882a593Smuzhiyun An AFU may have an MMIO space to facilitate communication with the 252*4882a593Smuzhiyun AFU. If it does, the MMIO space can be accessed via mmap. The size 253*4882a593Smuzhiyun and contents of this area are specific to the particular AFU. The 254*4882a593Smuzhiyun size can be discovered via sysfs. 255*4882a593Smuzhiyun 256*4882a593Smuzhiyun In AFU directed mode, master contexts are allowed to map all of 257*4882a593Smuzhiyun the MMIO space and slave contexts are allowed to only map the per 258*4882a593Smuzhiyun process MMIO space associated with the context. In dedicated 259*4882a593Smuzhiyun process mode the entire MMIO space can always be mapped. 260*4882a593Smuzhiyun 261*4882a593Smuzhiyun This mmap call must be done after the START_WORK ioctl. 262*4882a593Smuzhiyun 263*4882a593Smuzhiyun Care should be taken when accessing MMIO space. Only 32 and 64-bit 264*4882a593Smuzhiyun accesses are supported by POWER8. Also, the AFU will be designed 265*4882a593Smuzhiyun with a specific endianness, so all MMIO accesses should consider 266*4882a593Smuzhiyun endianness (recommend endian(3) variants like: le64toh(), 267*4882a593Smuzhiyun be64toh() etc). These endian issues equally apply to shared memory 268*4882a593Smuzhiyun queues the WED may describe. 269*4882a593Smuzhiyun 270*4882a593Smuzhiyun 271*4882a593Smuzhiyunread 272*4882a593Smuzhiyun---- 273*4882a593Smuzhiyun 274*4882a593Smuzhiyun Reads events from the AFU. Blocks if no events are pending 275*4882a593Smuzhiyun (unless O_NONBLOCK is supplied). Returns -EIO in the case of an 276*4882a593Smuzhiyun unrecoverable error or if the card is removed. 277*4882a593Smuzhiyun 278*4882a593Smuzhiyun read() will always return an integral number of events. 279*4882a593Smuzhiyun 280*4882a593Smuzhiyun The buffer passed to read() must be at least 4K bytes. 281*4882a593Smuzhiyun 282*4882a593Smuzhiyun The result of the read will be a buffer of one or more events, 283*4882a593Smuzhiyun each event is of type struct cxl_event, of varying size:: 284*4882a593Smuzhiyun 285*4882a593Smuzhiyun struct cxl_event { 286*4882a593Smuzhiyun struct cxl_event_header header; 287*4882a593Smuzhiyun union { 288*4882a593Smuzhiyun struct cxl_event_afu_interrupt irq; 289*4882a593Smuzhiyun struct cxl_event_data_storage fault; 290*4882a593Smuzhiyun struct cxl_event_afu_error afu_error; 291*4882a593Smuzhiyun }; 292*4882a593Smuzhiyun }; 293*4882a593Smuzhiyun 294*4882a593Smuzhiyun The struct cxl_event_header is defined as 295*4882a593Smuzhiyun 296*4882a593Smuzhiyun :: 297*4882a593Smuzhiyun 298*4882a593Smuzhiyun struct cxl_event_header { 299*4882a593Smuzhiyun __u16 type; 300*4882a593Smuzhiyun __u16 size; 301*4882a593Smuzhiyun __u16 process_element; 302*4882a593Smuzhiyun __u16 reserved1; 303*4882a593Smuzhiyun }; 304*4882a593Smuzhiyun 305*4882a593Smuzhiyun type: 306*4882a593Smuzhiyun This defines the type of event. The type determines how 307*4882a593Smuzhiyun the rest of the event is structured. These types are 308*4882a593Smuzhiyun described below and defined by enum cxl_event_type. 309*4882a593Smuzhiyun 310*4882a593Smuzhiyun size: 311*4882a593Smuzhiyun This is the size of the event in bytes including the 312*4882a593Smuzhiyun struct cxl_event_header. The start of the next event can 313*4882a593Smuzhiyun be found at this offset from the start of the current 314*4882a593Smuzhiyun event. 315*4882a593Smuzhiyun 316*4882a593Smuzhiyun process_element: 317*4882a593Smuzhiyun Context ID of the event. 318*4882a593Smuzhiyun 319*4882a593Smuzhiyun reserved field: 320*4882a593Smuzhiyun For future extensions and padding. 321*4882a593Smuzhiyun 322*4882a593Smuzhiyun If the event type is CXL_EVENT_AFU_INTERRUPT then the event 323*4882a593Smuzhiyun structure is defined as 324*4882a593Smuzhiyun 325*4882a593Smuzhiyun :: 326*4882a593Smuzhiyun 327*4882a593Smuzhiyun struct cxl_event_afu_interrupt { 328*4882a593Smuzhiyun __u16 flags; 329*4882a593Smuzhiyun __u16 irq; /* Raised AFU interrupt number */ 330*4882a593Smuzhiyun __u32 reserved1; 331*4882a593Smuzhiyun }; 332*4882a593Smuzhiyun 333*4882a593Smuzhiyun flags: 334*4882a593Smuzhiyun These flags indicate which optional fields are present 335*4882a593Smuzhiyun in this struct. Currently all fields are mandatory. 336*4882a593Smuzhiyun 337*4882a593Smuzhiyun irq: 338*4882a593Smuzhiyun The IRQ number sent by the AFU. 339*4882a593Smuzhiyun 340*4882a593Smuzhiyun reserved field: 341*4882a593Smuzhiyun For future extensions and padding. 342*4882a593Smuzhiyun 343*4882a593Smuzhiyun If the event type is CXL_EVENT_DATA_STORAGE then the event 344*4882a593Smuzhiyun structure is defined as 345*4882a593Smuzhiyun 346*4882a593Smuzhiyun :: 347*4882a593Smuzhiyun 348*4882a593Smuzhiyun struct cxl_event_data_storage { 349*4882a593Smuzhiyun __u16 flags; 350*4882a593Smuzhiyun __u16 reserved1; 351*4882a593Smuzhiyun __u32 reserved2; 352*4882a593Smuzhiyun __u64 addr; 353*4882a593Smuzhiyun __u64 dsisr; 354*4882a593Smuzhiyun __u64 reserved3; 355*4882a593Smuzhiyun }; 356*4882a593Smuzhiyun 357*4882a593Smuzhiyun flags: 358*4882a593Smuzhiyun These flags indicate which optional fields are present in 359*4882a593Smuzhiyun this struct. Currently all fields are mandatory. 360*4882a593Smuzhiyun 361*4882a593Smuzhiyun address: 362*4882a593Smuzhiyun The address that the AFU unsuccessfully attempted to 363*4882a593Smuzhiyun access. Valid accesses will be handled transparently by the 364*4882a593Smuzhiyun kernel but invalid accesses will generate this event. 365*4882a593Smuzhiyun 366*4882a593Smuzhiyun dsisr: 367*4882a593Smuzhiyun This field gives information on the type of fault. It is a 368*4882a593Smuzhiyun copy of the DSISR from the PSL hardware when the address 369*4882a593Smuzhiyun fault occurred. The form of the DSISR is as defined in the 370*4882a593Smuzhiyun CAIA. 371*4882a593Smuzhiyun 372*4882a593Smuzhiyun reserved fields: 373*4882a593Smuzhiyun For future extensions 374*4882a593Smuzhiyun 375*4882a593Smuzhiyun If the event type is CXL_EVENT_AFU_ERROR then the event structure 376*4882a593Smuzhiyun is defined as 377*4882a593Smuzhiyun 378*4882a593Smuzhiyun :: 379*4882a593Smuzhiyun 380*4882a593Smuzhiyun struct cxl_event_afu_error { 381*4882a593Smuzhiyun __u16 flags; 382*4882a593Smuzhiyun __u16 reserved1; 383*4882a593Smuzhiyun __u32 reserved2; 384*4882a593Smuzhiyun __u64 error; 385*4882a593Smuzhiyun }; 386*4882a593Smuzhiyun 387*4882a593Smuzhiyun flags: 388*4882a593Smuzhiyun These flags indicate which optional fields are present in 389*4882a593Smuzhiyun this struct. Currently all fields are Mandatory. 390*4882a593Smuzhiyun 391*4882a593Smuzhiyun error: 392*4882a593Smuzhiyun Error status from the AFU. Defined by the AFU. 393*4882a593Smuzhiyun 394*4882a593Smuzhiyun reserved fields: 395*4882a593Smuzhiyun For future extensions and padding 396*4882a593Smuzhiyun 397*4882a593Smuzhiyun 398*4882a593Smuzhiyun2. Card character device (powerVM guest only) 399*4882a593Smuzhiyun^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 400*4882a593Smuzhiyun 401*4882a593Smuzhiyun In a powerVM guest, an extra character device is created for the 402*4882a593Smuzhiyun card. The device is only used to write (flash) a new image on the 403*4882a593Smuzhiyun FPGA accelerator. Once the image is written and verified, the 404*4882a593Smuzhiyun device tree is updated and the card is reset to reload the updated 405*4882a593Smuzhiyun image. 406*4882a593Smuzhiyun 407*4882a593Smuzhiyunopen 408*4882a593Smuzhiyun---- 409*4882a593Smuzhiyun 410*4882a593Smuzhiyun Opens the device and allocates a file descriptor to be used with 411*4882a593Smuzhiyun the rest of the API. The device can only be opened once. 412*4882a593Smuzhiyun 413*4882a593Smuzhiyunioctl 414*4882a593Smuzhiyun----- 415*4882a593Smuzhiyun 416*4882a593SmuzhiyunCXL_IOCTL_DOWNLOAD_IMAGE / CXL_IOCTL_VALIDATE_IMAGE: 417*4882a593Smuzhiyun Starts and controls flashing a new FPGA image. Partial 418*4882a593Smuzhiyun reconfiguration is not supported (yet), so the image must contain 419*4882a593Smuzhiyun a copy of the PSL and AFU(s). Since an image can be quite large, 420*4882a593Smuzhiyun the caller may have to iterate, splitting the image in smaller 421*4882a593Smuzhiyun chunks. 422*4882a593Smuzhiyun 423*4882a593Smuzhiyun Takes a pointer to a struct cxl_adapter_image:: 424*4882a593Smuzhiyun 425*4882a593Smuzhiyun struct cxl_adapter_image { 426*4882a593Smuzhiyun __u64 flags; 427*4882a593Smuzhiyun __u64 data; 428*4882a593Smuzhiyun __u64 len_data; 429*4882a593Smuzhiyun __u64 len_image; 430*4882a593Smuzhiyun __u64 reserved1; 431*4882a593Smuzhiyun __u64 reserved2; 432*4882a593Smuzhiyun __u64 reserved3; 433*4882a593Smuzhiyun __u64 reserved4; 434*4882a593Smuzhiyun }; 435*4882a593Smuzhiyun 436*4882a593Smuzhiyun flags: 437*4882a593Smuzhiyun These flags indicate which optional fields are present in 438*4882a593Smuzhiyun this struct. Currently all fields are mandatory. 439*4882a593Smuzhiyun 440*4882a593Smuzhiyun data: 441*4882a593Smuzhiyun Pointer to a buffer with part of the image to write to the 442*4882a593Smuzhiyun card. 443*4882a593Smuzhiyun 444*4882a593Smuzhiyun len_data: 445*4882a593Smuzhiyun Size of the buffer pointed to by data. 446*4882a593Smuzhiyun 447*4882a593Smuzhiyun len_image: 448*4882a593Smuzhiyun Full size of the image. 449*4882a593Smuzhiyun 450*4882a593Smuzhiyun 451*4882a593SmuzhiyunSysfs Class 452*4882a593Smuzhiyun=========== 453*4882a593Smuzhiyun 454*4882a593Smuzhiyun A cxl sysfs class is added under /sys/class/cxl to facilitate 455*4882a593Smuzhiyun enumeration and tuning of the accelerators. Its layout is 456*4882a593Smuzhiyun described in Documentation/ABI/testing/sysfs-class-cxl 457*4882a593Smuzhiyun 458*4882a593Smuzhiyun 459*4882a593SmuzhiyunUdev rules 460*4882a593Smuzhiyun========== 461*4882a593Smuzhiyun 462*4882a593Smuzhiyun The following udev rules could be used to create a symlink to the 463*4882a593Smuzhiyun most logical chardev to use in any programming mode (afuX.Yd for 464*4882a593Smuzhiyun dedicated, afuX.Ys for afu directed), since the API is virtually 465*4882a593Smuzhiyun identical for each:: 466*4882a593Smuzhiyun 467*4882a593Smuzhiyun SUBSYSTEM=="cxl", ATTRS{mode}=="dedicated_process", SYMLINK="cxl/%b" 468*4882a593Smuzhiyun SUBSYSTEM=="cxl", ATTRS{mode}=="afu_directed", \ 469*4882a593Smuzhiyun KERNEL=="afu[0-9]*.[0-9]*s", SYMLINK="cxl/%b" 470