1*4882a593Smuzhiyun.. SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun=============================================== 4*4882a593SmuzhiyunIngenic JZ47xx SoCs Timer/Counter Unit hardware 5*4882a593Smuzhiyun=============================================== 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunThe Timer/Counter Unit (TCU) in Ingenic JZ47xx SoCs is a multi-function 8*4882a593Smuzhiyunhardware block. It features up to eight channels, that can be used as 9*4882a593Smuzhiyuncounters, timers, or PWM. 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun- JZ4725B, JZ4750, JZ4755 only have six TCU channels. The other SoCs all 12*4882a593Smuzhiyun have eight channels. 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun- JZ4725B introduced a separate channel, called Operating System Timer 15*4882a593Smuzhiyun (OST). It is a 32-bit programmable timer. On JZ4760B and above, it is 16*4882a593Smuzhiyun 64-bit. 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun- Each one of the TCU channels has its own clock, which can be reparented to three 19*4882a593Smuzhiyun different clocks (pclk, ext, rtc), gated, and reclocked, through their TCSR register. 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun - The watchdog and OST hardware blocks also feature a TCSR register with the same 22*4882a593Smuzhiyun format in their register space. 23*4882a593Smuzhiyun - The TCU registers used to gate/ungate can also gate/ungate the watchdog and 24*4882a593Smuzhiyun OST clocks. 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun- Each TCU channel works in one of two modes: 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun - mode TCU1: channels cannot work in sleep mode, but are easier to 29*4882a593Smuzhiyun operate. 30*4882a593Smuzhiyun - mode TCU2: channels can work in sleep mode, but the operation is a bit 31*4882a593Smuzhiyun more complicated than with TCU1 channels. 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun- The mode of each TCU channel depends on the SoC used: 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun - On the oldest SoCs (up to JZ4740), all of the eight channels operate in 36*4882a593Smuzhiyun TCU1 mode. 37*4882a593Smuzhiyun - On JZ4725B, channel 5 operates as TCU2, the others operate as TCU1. 38*4882a593Smuzhiyun - On newest SoCs (JZ4750 and above), channels 1-2 operate as TCU2, the 39*4882a593Smuzhiyun others operate as TCU1. 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun- Each channel can generate an interrupt. Some channels share an interrupt 42*4882a593Smuzhiyun line, some don't, and this changes between SoC versions: 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun - on older SoCs (JZ4740 and below), channel 0 and channel 1 have their 45*4882a593Smuzhiyun own interrupt line; channels 2-7 share the last interrupt line. 46*4882a593Smuzhiyun - On JZ4725B, channel 0 has its own interrupt; channels 1-5 share one 47*4882a593Smuzhiyun interrupt line; the OST uses the last interrupt line. 48*4882a593Smuzhiyun - on newer SoCs (JZ4750 and above), channel 5 has its own interrupt; 49*4882a593Smuzhiyun channels 0-4 and (if eight channels) 6-7 all share one interrupt line; 50*4882a593Smuzhiyun the OST uses the last interrupt line. 51*4882a593Smuzhiyun 52*4882a593SmuzhiyunImplementation 53*4882a593Smuzhiyun============== 54*4882a593Smuzhiyun 55*4882a593SmuzhiyunThe functionalities of the TCU hardware are spread across multiple drivers: 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun=========== ===== 58*4882a593Smuzhiyunclocks drivers/clk/ingenic/tcu.c 59*4882a593Smuzhiyuninterrupts drivers/irqchip/irq-ingenic-tcu.c 60*4882a593Smuzhiyuntimers drivers/clocksource/ingenic-timer.c 61*4882a593SmuzhiyunOST drivers/clocksource/ingenic-ost.c 62*4882a593SmuzhiyunPWM drivers/pwm/pwm-jz4740.c 63*4882a593Smuzhiyunwatchdog drivers/watchdog/jz4740_wdt.c 64*4882a593Smuzhiyun=========== ===== 65*4882a593Smuzhiyun 66*4882a593SmuzhiyunBecause various functionalities of the TCU that belong to different drivers 67*4882a593Smuzhiyunand frameworks can be controlled from the same registers, all of these 68*4882a593Smuzhiyundrivers access their registers through the same regmap. 69*4882a593Smuzhiyun 70*4882a593SmuzhiyunFor more information regarding the devicetree bindings of the TCU drivers, 71*4882a593Smuzhiyunhave a look at Documentation/devicetree/bindings/timer/ingenic,tcu.yaml. 72