1*4882a593Smuzhiyun============================== 2*4882a593SmuzhiyunIRQ affinity on IA64 platforms 3*4882a593Smuzhiyun============================== 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun07.01.2002, Erich Focht <efocht@ess.nec.de> 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunBy writing to /proc/irq/IRQ#/smp_affinity the interrupt routing can be 9*4882a593Smuzhiyuncontrolled. The behavior on IA64 platforms is slightly different from 10*4882a593Smuzhiyunthat described in Documentation/core-api/irq/irq-affinity.rst for i386 systems. 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunBecause of the usage of SAPIC mode and physical destination mode the 13*4882a593SmuzhiyunIRQ target is one particular CPU and cannot be a mask of several 14*4882a593SmuzhiyunCPUs. Only the first non-zero bit is taken into account. 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunUsage examples 18*4882a593Smuzhiyun============== 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunThe target CPU has to be specified as a hexadecimal CPU mask. The 21*4882a593Smuzhiyunfirst non-zero bit is the selected CPU. This format has been kept for 22*4882a593Smuzhiyuncompatibility reasons with i386. 23*4882a593Smuzhiyun 24*4882a593SmuzhiyunSet the delivery mode of interrupt 41 to fixed and route the 25*4882a593Smuzhiyuninterrupts to CPU #3 (logical CPU number) (2^3=0x08):: 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun echo "8" >/proc/irq/41/smp_affinity 28*4882a593Smuzhiyun 29*4882a593SmuzhiyunSet the default route for IRQ number 41 to CPU 6 in lowest priority 30*4882a593Smuzhiyundelivery mode (redirectable):: 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun echo "r 40" >/proc/irq/41/smp_affinity 33*4882a593Smuzhiyun 34*4882a593SmuzhiyunThe output of the command:: 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun cat /proc/irq/IRQ#/smp_affinity 37*4882a593Smuzhiyun 38*4882a593Smuzhiyungives the target CPU mask for the specified interrupt vector. If the CPU 39*4882a593Smuzhiyunmask is preceded by the character "r", the interrupt is redirectable 40*4882a593Smuzhiyun(i.e. lowest priority mode routing is used), otherwise its route is 41*4882a593Smuzhiyunfixed. 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun 45*4882a593SmuzhiyunInitialization and default behavior 46*4882a593Smuzhiyun=================================== 47*4882a593Smuzhiyun 48*4882a593SmuzhiyunIf the platform features IRQ redirection (info provided by SAL) all 49*4882a593SmuzhiyunIO-SAPIC interrupts are initialized with CPU#0 as their default target 50*4882a593Smuzhiyunand the routing is the so called "lowest priority mode" (actually 51*4882a593Smuzhiyunfixed SAPIC mode with hint). The XTP chipset registers are used as hints 52*4882a593Smuzhiyunfor the IRQ routing. Currently in Linux XTP registers can have three 53*4882a593Smuzhiyunvalues: 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun - minimal for an idle task, 56*4882a593Smuzhiyun - normal if any other task runs, 57*4882a593Smuzhiyun - maximal if the CPU is going to be switched off. 58*4882a593Smuzhiyun 59*4882a593SmuzhiyunThe IRQ is routed to the CPU with lowest XTP register value, the 60*4882a593Smuzhiyunsearch begins at the default CPU. Therefore most of the interrupts 61*4882a593Smuzhiyunwill be handled by CPU #0. 62*4882a593Smuzhiyun 63*4882a593SmuzhiyunIf the platform doesn't feature interrupt redirection IOSAPIC fixed 64*4882a593Smuzhiyunrouting is used. The target CPUs are distributed in a round robin 65*4882a593Smuzhiyunmanner. IRQs will be routed only to the selected target CPUs. Check 66*4882a593Smuzhiyunwith:: 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun cat /proc/interrupts 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun 72*4882a593SmuzhiyunComments 73*4882a593Smuzhiyun======== 74*4882a593Smuzhiyun 75*4882a593SmuzhiyunOn large (multi-node) systems it is recommended to route the IRQs to 76*4882a593Smuzhiyunthe node to which the corresponding device is connected. 77*4882a593SmuzhiyunFor systems like the NEC AzusA we get IRQ node-affinity for free. This 78*4882a593Smuzhiyunis because usually the chipsets on each node redirect the interrupts 79*4882a593Smuzhiyunonly to their own CPUs (as they cannot see the XTP registers on the 80*4882a593Smuzhiyunother nodes). 81