1*4882a593Smuzhiyun===================================== 2*4882a593SmuzhiyunLinux I2C slave interface description 3*4882a593Smuzhiyun===================================== 4*4882a593Smuzhiyun 5*4882a593Smuzhiyunby Wolfram Sang <wsa@sang-engineering.com> in 2014-15 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunLinux can also be an I2C slave if the I2C controller in use has slave 8*4882a593Smuzhiyunfunctionality. For that to work, one needs slave support in the bus driver plus 9*4882a593Smuzhiyuna hardware independent software backend providing the actual functionality. An 10*4882a593Smuzhiyunexample for the latter is the slave-eeprom driver, which acts as a dual memory 11*4882a593Smuzhiyundriver. While another I2C master on the bus can access it like a regular 12*4882a593SmuzhiyunEEPROM, the Linux I2C slave can access the content via sysfs and handle data as 13*4882a593Smuzhiyunneeded. The backend driver and the I2C bus driver communicate via events. Here 14*4882a593Smuzhiyunis a small graph visualizing the data flow and the means by which data is 15*4882a593Smuzhiyuntransported. The dotted line marks only one example. The backend could also 16*4882a593Smuzhiyunuse a character device, be in-kernel only, or something completely different:: 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun e.g. sysfs I2C slave events I/O registers 20*4882a593Smuzhiyun +-----------+ v +---------+ v +--------+ v +------------+ 21*4882a593Smuzhiyun | Userspace +........+ Backend +-----------+ Driver +-----+ Controller | 22*4882a593Smuzhiyun +-----------+ +---------+ +--------+ +------------+ 23*4882a593Smuzhiyun | | 24*4882a593Smuzhiyun ----------------------------------------------------------------+-- I2C 25*4882a593Smuzhiyun --------------------------------------------------------------+---- Bus 26*4882a593Smuzhiyun 27*4882a593SmuzhiyunNote: Technically, there is also the I2C core between the backend and the 28*4882a593Smuzhiyundriver. However, at this time of writing, the layer is transparent. 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun 31*4882a593SmuzhiyunUser manual 32*4882a593Smuzhiyun=========== 33*4882a593Smuzhiyun 34*4882a593SmuzhiyunI2C slave backends behave like standard I2C clients. So, you can instantiate 35*4882a593Smuzhiyunthem as described in the document 'instantiating-devices'. The only difference 36*4882a593Smuzhiyunis that i2c slave backends have their own address space. So, you have to add 37*4882a593Smuzhiyun0x1000 to the address you would originally request. An example for 38*4882a593Smuzhiyuninstantiating the slave-eeprom driver from userspace at the 7 bit address 0x64 39*4882a593Smuzhiyunon bus 1:: 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun # echo slave-24c02 0x1064 > /sys/bus/i2c/devices/i2c-1/new_device 42*4882a593Smuzhiyun 43*4882a593SmuzhiyunEach backend should come with separate documentation to describe its specific 44*4882a593Smuzhiyunbehaviour and setup. 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun 47*4882a593SmuzhiyunDeveloper manual 48*4882a593Smuzhiyun================ 49*4882a593Smuzhiyun 50*4882a593SmuzhiyunFirst, the events which are used by the bus driver and the backend will be 51*4882a593Smuzhiyundescribed in detail. After that, some implementation hints for extending bus 52*4882a593Smuzhiyundrivers and writing backends will be given. 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun 55*4882a593SmuzhiyunI2C slave events 56*4882a593Smuzhiyun---------------- 57*4882a593Smuzhiyun 58*4882a593SmuzhiyunThe bus driver sends an event to the backend using the following function:: 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun ret = i2c_slave_event(client, event, &val) 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun'client' describes the I2C slave device. 'event' is one of the special event 63*4882a593Smuzhiyuntypes described hereafter. 'val' holds an u8 value for the data byte to be 64*4882a593Smuzhiyunread/written and is thus bidirectional. The pointer to val must always be 65*4882a593Smuzhiyunprovided even if val is not used for an event, i.e. don't use NULL here. 'ret' 66*4882a593Smuzhiyunis the return value from the backend. Mandatory events must be provided by the 67*4882a593Smuzhiyunbus drivers and must be checked for by backend drivers. 68*4882a593Smuzhiyun 69*4882a593SmuzhiyunEvent types: 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun* I2C_SLAVE_WRITE_REQUESTED (mandatory) 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun 'val': unused 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun 'ret': always 0 76*4882a593Smuzhiyun 77*4882a593SmuzhiyunAnother I2C master wants to write data to us. This event should be sent once 78*4882a593Smuzhiyunour own address and the write bit was detected. The data did not arrive yet, so 79*4882a593Smuzhiyunthere is nothing to process or return. Wakeup or initialization probably needs 80*4882a593Smuzhiyunto be done, though. 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun* I2C_SLAVE_READ_REQUESTED (mandatory) 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun 'val': backend returns first byte to be sent 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun 'ret': always 0 87*4882a593Smuzhiyun 88*4882a593SmuzhiyunAnother I2C master wants to read data from us. This event should be sent once 89*4882a593Smuzhiyunour own address and the read bit was detected. After returning, the bus driver 90*4882a593Smuzhiyunshould transmit the first byte. 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun* I2C_SLAVE_WRITE_RECEIVED (mandatory) 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun 'val': bus driver delivers received byte 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun 'ret': 0 if the byte should be acked, some errno if the byte should be nacked 97*4882a593Smuzhiyun 98*4882a593SmuzhiyunAnother I2C master has sent a byte to us which needs to be set in 'val'. If 'ret' 99*4882a593Smuzhiyunis zero, the bus driver should ack this byte. If 'ret' is an errno, then the byte 100*4882a593Smuzhiyunshould be nacked. 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun* I2C_SLAVE_READ_PROCESSED (mandatory) 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun 'val': backend returns next byte to be sent 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun 'ret': always 0 107*4882a593Smuzhiyun 108*4882a593SmuzhiyunThe bus driver requests the next byte to be sent to another I2C master in 109*4882a593Smuzhiyun'val'. Important: This does not mean that the previous byte has been acked, it 110*4882a593Smuzhiyunonly means that the previous byte is shifted out to the bus! To ensure seamless 111*4882a593Smuzhiyuntransmission, most hardware requests the next byte when the previous one is 112*4882a593Smuzhiyunstill shifted out. If the master sends NACK and stops reading after the byte 113*4882a593Smuzhiyuncurrently shifted out, this byte requested here is never used. It very likely 114*4882a593Smuzhiyunneeds to be sent again on the next I2C_SLAVE_READ_REQUEST, depending a bit on 115*4882a593Smuzhiyunyour backend, though. 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun* I2C_SLAVE_STOP (mandatory) 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun 'val': unused 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun 'ret': always 0 122*4882a593Smuzhiyun 123*4882a593SmuzhiyunA stop condition was received. This can happen anytime and the backend should 124*4882a593Smuzhiyunreset its state machine for I2C transfers to be able to receive new requests. 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun 127*4882a593SmuzhiyunSoftware backends 128*4882a593Smuzhiyun----------------- 129*4882a593Smuzhiyun 130*4882a593SmuzhiyunIf you want to write a software backend: 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun* use a standard i2c_driver and its matching mechanisms 133*4882a593Smuzhiyun* write the slave_callback which handles the above slave events 134*4882a593Smuzhiyun (best using a state machine) 135*4882a593Smuzhiyun* register this callback via i2c_slave_register() 136*4882a593Smuzhiyun 137*4882a593SmuzhiyunCheck the i2c-slave-eeprom driver as an example. 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun 140*4882a593SmuzhiyunBus driver support 141*4882a593Smuzhiyun------------------ 142*4882a593Smuzhiyun 143*4882a593SmuzhiyunIf you want to add slave support to the bus driver: 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun* implement calls to register/unregister the slave and add those to the 146*4882a593Smuzhiyun struct i2c_algorithm. When registering, you probably need to set the I2C 147*4882a593Smuzhiyun slave address and enable slave specific interrupts. If you use runtime pm, you 148*4882a593Smuzhiyun should use pm_runtime_get_sync() because your device usually needs to be 149*4882a593Smuzhiyun powered on always to be able to detect its slave address. When unregistering, 150*4882a593Smuzhiyun do the inverse of the above. 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun* Catch the slave interrupts and send appropriate i2c_slave_events to the backend. 153*4882a593Smuzhiyun 154*4882a593SmuzhiyunNote that most hardware supports being master _and_ slave on the same bus. So, 155*4882a593Smuzhiyunif you extend a bus driver, please make sure that the driver supports that as 156*4882a593Smuzhiyunwell. In almost all cases, slave support does not need to disable the master 157*4882a593Smuzhiyunfunctionality. 158*4882a593Smuzhiyun 159*4882a593SmuzhiyunCheck the i2c-rcar driver as an example. 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun 162*4882a593SmuzhiyunAbout ACK/NACK 163*4882a593Smuzhiyun-------------- 164*4882a593Smuzhiyun 165*4882a593SmuzhiyunIt is good behaviour to always ACK the address phase, so the master knows if a 166*4882a593Smuzhiyundevice is basically present or if it mysteriously disappeared. Using NACK to 167*4882a593Smuzhiyunstate being busy is troublesome. SMBus demands to always ACK the address phase, 168*4882a593Smuzhiyunwhile the I2C specification is more loose on that. Most I2C controllers also 169*4882a593Smuzhiyunautomatically ACK when detecting their slave addresses, so there is no option 170*4882a593Smuzhiyunto NACK them. For those reasons, this API does not support NACK in the address 171*4882a593Smuzhiyunphase. 172*4882a593Smuzhiyun 173*4882a593SmuzhiyunCurrently, there is no slave event to report if the master did ACK or NACK a 174*4882a593Smuzhiyunbyte when it reads from us. We could make this an optional event if the need 175*4882a593Smuzhiyunarises. However, cases should be extremely rare because the master is expected 176*4882a593Smuzhiyunto send STOP after that and we have an event for that. Also, keep in mind not 177*4882a593Smuzhiyunall I2C controllers have the possibility to report that event. 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun 180*4882a593SmuzhiyunAbout buffers 181*4882a593Smuzhiyun------------- 182*4882a593Smuzhiyun 183*4882a593SmuzhiyunDuring development of this API, the question of using buffers instead of just 184*4882a593Smuzhiyunbytes came up. Such an extension might be possible, usefulness is unclear at 185*4882a593Smuzhiyunthis time of writing. Some points to keep in mind when using buffers: 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun* Buffers should be opt-in and backend drivers will always have to support 188*4882a593Smuzhiyun byte-based transactions as the ultimate fallback anyhow because this is how 189*4882a593Smuzhiyun the majority of HW works. 190*4882a593Smuzhiyun 191*4882a593Smuzhiyun* For backends simulating hardware registers, buffers are largely not helpful 192*4882a593Smuzhiyun because after each byte written an action should be immediately triggered. 193*4882a593Smuzhiyun For reads, the data kept in the buffer might get stale if the backend just 194*4882a593Smuzhiyun updated a register because of internal processing. 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun* A master can send STOP at any time. For partially transferred buffers, this 197*4882a593Smuzhiyun means additional code to handle this exception. Such code tends to be 198*4882a593Smuzhiyun error-prone. 199