1*4882a593Smuzhiyun================ 2*4882a593SmuzhiyunThe I2C Protocol 3*4882a593Smuzhiyun================ 4*4882a593Smuzhiyun 5*4882a593SmuzhiyunThis document describes the I2C protocol. Or will, when it is finished :-) 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunKey to symbols 8*4882a593Smuzhiyun============== 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun=============== ============================================================= 11*4882a593SmuzhiyunS Start condition 12*4882a593SmuzhiyunP Stop condition 13*4882a593SmuzhiyunRd/Wr (1 bit) Read/Write bit. Rd equals 1, Wr equals 0. 14*4882a593SmuzhiyunA, NA (1 bit) Acknowledge (ACK) and Not Acknowledge (NACK) bit 15*4882a593SmuzhiyunAddr (7 bits) I2C 7 bit address. Note that this can be expanded as usual to 16*4882a593Smuzhiyun get a 10 bit I2C address. 17*4882a593SmuzhiyunComm (8 bits) Command byte, a data byte which often selects a register on 18*4882a593Smuzhiyun the device. 19*4882a593SmuzhiyunData (8 bits) A plain data byte. Sometimes, I write DataLow, DataHigh 20*4882a593Smuzhiyun for 16 bit data. 21*4882a593SmuzhiyunCount (8 bits) A data byte containing the length of a block operation. 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun[..] Data sent by I2C device, as opposed to data sent by the 24*4882a593Smuzhiyun host adapter. 25*4882a593Smuzhiyun=============== ============================================================= 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun 28*4882a593SmuzhiyunSimple send transaction 29*4882a593Smuzhiyun======================= 30*4882a593Smuzhiyun 31*4882a593SmuzhiyunImplemented by i2c_master_send():: 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun S Addr Wr [A] Data [A] Data [A] ... [A] Data [A] P 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun 36*4882a593SmuzhiyunSimple receive transaction 37*4882a593Smuzhiyun========================== 38*4882a593Smuzhiyun 39*4882a593SmuzhiyunImplemented by i2c_master_recv():: 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun S Addr Rd [A] [Data] A [Data] A ... A [Data] NA P 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun 44*4882a593SmuzhiyunCombined transactions 45*4882a593Smuzhiyun===================== 46*4882a593Smuzhiyun 47*4882a593SmuzhiyunImplemented by i2c_transfer(). 48*4882a593Smuzhiyun 49*4882a593SmuzhiyunThey are just like the above transactions, but instead of a stop 50*4882a593Smuzhiyuncondition P a start condition S is sent and the transaction continues. 51*4882a593SmuzhiyunAn example of a byte read, followed by a byte write:: 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun S Addr Rd [A] [Data] NA S Addr Wr [A] Data [A] P 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun 56*4882a593SmuzhiyunModified transactions 57*4882a593Smuzhiyun===================== 58*4882a593Smuzhiyun 59*4882a593SmuzhiyunThe following modifications to the I2C protocol can also be generated by 60*4882a593Smuzhiyunsetting these flags for I2C messages. With the exception of I2C_M_NOSTART, they 61*4882a593Smuzhiyunare usually only needed to work around device issues: 62*4882a593Smuzhiyun 63*4882a593SmuzhiyunI2C_M_IGNORE_NAK: 64*4882a593Smuzhiyun Normally message is interrupted immediately if there is [NA] from the 65*4882a593Smuzhiyun client. Setting this flag treats any [NA] as [A], and all of 66*4882a593Smuzhiyun message is sent. 67*4882a593Smuzhiyun These messages may still fail to SCL lo->hi timeout. 68*4882a593Smuzhiyun 69*4882a593SmuzhiyunI2C_M_NO_RD_ACK: 70*4882a593Smuzhiyun In a read message, master A/NA bit is skipped. 71*4882a593Smuzhiyun 72*4882a593SmuzhiyunI2C_M_NOSTART: 73*4882a593Smuzhiyun In a combined transaction, no 'S Addr Wr/Rd [A]' is generated at some 74*4882a593Smuzhiyun point. For example, setting I2C_M_NOSTART on the second partial message 75*4882a593Smuzhiyun generates something like:: 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun S Addr Rd [A] [Data] NA Data [A] P 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun If you set the I2C_M_NOSTART variable for the first partial message, 80*4882a593Smuzhiyun we do not generate Addr, but we do generate the start condition S. 81*4882a593Smuzhiyun This will probably confuse all other clients on your bus, so don't 82*4882a593Smuzhiyun try this. 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun This is often used to gather transmits from multiple data buffers in 85*4882a593Smuzhiyun system memory into something that appears as a single transfer to the 86*4882a593Smuzhiyun I2C device but may also be used between direction changes by some 87*4882a593Smuzhiyun rare devices. 88*4882a593Smuzhiyun 89*4882a593SmuzhiyunI2C_M_REV_DIR_ADDR: 90*4882a593Smuzhiyun This toggles the Rd/Wr flag. That is, if you want to do a write, but 91*4882a593Smuzhiyun need to emit an Rd instead of a Wr, or vice versa, you set this 92*4882a593Smuzhiyun flag. For example:: 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun S Addr Rd [A] Data [A] Data [A] ... [A] Data [A] P 95*4882a593Smuzhiyun 96*4882a593SmuzhiyunI2C_M_STOP: 97*4882a593Smuzhiyun Force a stop condition (P) after the message. Some I2C related protocols 98*4882a593Smuzhiyun like SCCB require that. Normally, you really don't want to get interrupted 99*4882a593Smuzhiyun between the messages of one transfer. 100