1*4882a593Smuzhiyun================== 2*4882a593SmuzhiyunDriver i2c-mlxcpld 3*4882a593Smuzhiyun================== 4*4882a593Smuzhiyun 5*4882a593SmuzhiyunAuthor: Michael Shych <michaelsh@mellanox.com> 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunThis is the Mellanox I2C controller logic, implemented in Lattice CPLD 8*4882a593Smuzhiyundevice. 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunDevice supports: 11*4882a593Smuzhiyun - Master mode. 12*4882a593Smuzhiyun - One physical bus. 13*4882a593Smuzhiyun - Polling mode. 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunThis controller is equipped within the next Mellanox systems: 16*4882a593Smuzhiyun"msx6710", "msx6720", "msb7700", "msn2700", "msx1410", "msn2410", "msb7800", 17*4882a593Smuzhiyun"msn2740", "msn2100". 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunThe next transaction types are supported: 20*4882a593Smuzhiyun - Receive Byte/Block. 21*4882a593Smuzhiyun - Send Byte/Block. 22*4882a593Smuzhiyun - Read Byte/Block. 23*4882a593Smuzhiyun - Write Byte/Block. 24*4882a593Smuzhiyun 25*4882a593SmuzhiyunRegisters: 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun=============== === ======================================================================= 28*4882a593SmuzhiyunCPBLTY 0x0 - capability reg. 29*4882a593Smuzhiyun Bits [6:5] - transaction length. b01 - 72B is supported, 30*4882a593Smuzhiyun 36B in other case. 31*4882a593Smuzhiyun Bit 7 - SMBus block read support. 32*4882a593SmuzhiyunCTRL 0x1 - control reg. 33*4882a593Smuzhiyun Resets all the registers. 34*4882a593SmuzhiyunHALF_CYC 0x4 - cycle reg. 35*4882a593Smuzhiyun Configure the width of I2C SCL half clock cycle (in 4 LPC_CLK 36*4882a593Smuzhiyun units). 37*4882a593SmuzhiyunI2C_HOLD 0x5 - hold reg. 38*4882a593Smuzhiyun OE (output enable) is delayed by value set to this register 39*4882a593Smuzhiyun (in LPC_CLK units) 40*4882a593SmuzhiyunCMD 0x6 - command reg. 41*4882a593Smuzhiyun Bit 0, 0 = write, 1 = read. 42*4882a593Smuzhiyun Bits [7:1] - the 7bit Address of the I2C device. 43*4882a593Smuzhiyun It should be written last as it triggers an I2C transaction. 44*4882a593SmuzhiyunNUM_DATA 0x7 - data size reg. 45*4882a593Smuzhiyun Number of data bytes to write in read transaction 46*4882a593SmuzhiyunNUM_ADDR 0x8 - address reg. 47*4882a593Smuzhiyun Number of address bytes to write in read transaction. 48*4882a593SmuzhiyunSTATUS 0x9 - status reg. 49*4882a593Smuzhiyun Bit 0 - transaction is completed. 50*4882a593Smuzhiyun Bit 4 - ACK/NACK. 51*4882a593SmuzhiyunDATAx 0xa - 0x54 - 68 bytes data buffer regs. 52*4882a593Smuzhiyun For write transaction address is specified in four first bytes 53*4882a593Smuzhiyun (DATA1 - DATA4), data starting from DATA4. 54*4882a593Smuzhiyun For read transactions address is sent in a separate transaction and 55*4882a593Smuzhiyun specified in the four first bytes (DATA0 - DATA3). Data is read 56*4882a593Smuzhiyun starting from DATA0. 57*4882a593Smuzhiyun=============== === ======================================================================= 58