1*4882a593SmuzhiyunKernel driver nsa320_hwmon 2*4882a593Smuzhiyun========================== 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunSupported chips: 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun * Holtek HT46R065 microcontroller with onboard firmware that configures 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun it to act as a hardware monitor. 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun Prefix: 'nsa320' 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun Addresses scanned: none 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun Datasheet: Not available, driver was reverse engineered based upon the 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun Zyxel kernel source 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunAuthor: 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun Adam Baker <linux@baker-net.org.uk> 23*4882a593Smuzhiyun 24*4882a593SmuzhiyunDescription 25*4882a593Smuzhiyun----------- 26*4882a593Smuzhiyun 27*4882a593SmuzhiyunThis chip is known to be used in the Zyxel NSA320 and NSA325 NAS Units and 28*4882a593Smuzhiyunalso in some variants of the NSA310 but the driver has only been tested 29*4882a593Smuzhiyunon the NSA320. In all of these devices it is connected to the same 3 GPIO 30*4882a593Smuzhiyunlines which are used to provide chip select, clock and data lines. The 31*4882a593Smuzhiyuninterface behaves similarly to SPI but at much lower speeds than are normally 32*4882a593Smuzhiyunused for SPI. 33*4882a593Smuzhiyun 34*4882a593SmuzhiyunFollowing each chip select pulse the chip will generate a single 32 bit word 35*4882a593Smuzhiyunthat contains 0x55 as a marker to indicate that data is being read correctly, 36*4882a593Smuzhiyunfollowed by an 8 bit fan speed in 100s of RPM and a 16 bit temperature in 37*4882a593Smuzhiyuntenths of a degree. 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun 40*4882a593Smuzhiyunsysfs-Interface 41*4882a593Smuzhiyun--------------- 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun============= ================= 44*4882a593Smuzhiyuntemp1_input temperature input 45*4882a593Smuzhiyunfan1_input fan speed 46*4882a593Smuzhiyun============= ================= 47*4882a593Smuzhiyun 48*4882a593SmuzhiyunNotes 49*4882a593Smuzhiyun----- 50*4882a593Smuzhiyun 51*4882a593SmuzhiyunThe access timings used in the driver are the same as used in the Zyxel 52*4882a593Smuzhiyunprovided kernel. Testing has shown that if the delay between chip select and 53*4882a593Smuzhiyunthe first clock pulse is reduced from 100 ms to just under 10ms then the chip 54*4882a593Smuzhiyunwill not produce any output. If the duration of either phase of the clock 55*4882a593Smuzhiyunis reduced from 100 us to less than 15 us then data pulses are likely to be 56*4882a593Smuzhiyunread twice corrupting the output. The above analysis is based upon a sample 57*4882a593Smuzhiyunof one unit but suggests that the Zyxel provided delay values include a 58*4882a593Smuzhiyunreasonable tolerance. 59*4882a593Smuzhiyun 60*4882a593SmuzhiyunThe driver incorporates a limit that it will not check for updated values 61*4882a593Smuzhiyunfaster than once a second. This is because the hardware takes a relatively long 62*4882a593Smuzhiyuntime to read the data from the device and when it does it reads both temp and 63*4882a593Smuzhiyunfan speed. As the most likely case for two accesses in quick succession is 64*4882a593Smuzhiyunto read both of these values avoiding a second read delay is desirable. 65