1*4882a593Smuzhiyundigraph T { 2*4882a593Smuzhiyun /* Make sure our payloads are always drawn below the driver node */ 3*4882a593Smuzhiyun subgraph cluster_driver { 4*4882a593Smuzhiyun fillcolor = grey; 5*4882a593Smuzhiyun style = filled; 6*4882a593Smuzhiyun driver -> {payload1, payload2} [dir=none]; 7*4882a593Smuzhiyun } 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* Driver malloc references */ 10*4882a593Smuzhiyun edge [style=dashed]; 11*4882a593Smuzhiyun driver -> port1; 12*4882a593Smuzhiyun driver -> port2; 13*4882a593Smuzhiyun driver -> port3:e; 14*4882a593Smuzhiyun driver -> port4; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun payload1:s -> port1:e; 17*4882a593Smuzhiyun payload2:s -> port3:e; 18*4882a593Smuzhiyun edge [style=""]; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun subgraph cluster_topology { 21*4882a593Smuzhiyun label="Topology Manager"; 22*4882a593Smuzhiyun labelloc=bottom; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* Topology references */ 25*4882a593Smuzhiyun mstb1 -> {port1, port2}; 26*4882a593Smuzhiyun port1 -> mstb2; 27*4882a593Smuzhiyun port2 -> mstb3 -> {port3, port4}; 28*4882a593Smuzhiyun port3 -> mstb4; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* Malloc references */ 31*4882a593Smuzhiyun edge [style=dashed;dir=back]; 32*4882a593Smuzhiyun mstb1 -> {port1, port2}; 33*4882a593Smuzhiyun port1 -> mstb2; 34*4882a593Smuzhiyun port2 -> mstb3 -> {port3, port4}; 35*4882a593Smuzhiyun port3 -> mstb4; 36*4882a593Smuzhiyun } 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun driver [label="DRM driver";style=filled;shape=box;fillcolor=lightblue]; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun payload1 [label="Payload #1";style=filled;shape=box;fillcolor=lightblue]; 41*4882a593Smuzhiyun payload2 [label="Payload #2";style=filled;shape=box;fillcolor=lightblue]; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun mstb1 [label="MSTB #1";style=filled;fillcolor=palegreen;shape=oval]; 44*4882a593Smuzhiyun mstb2 [label="MSTB #2";style=filled;fillcolor=palegreen;shape=oval]; 45*4882a593Smuzhiyun mstb3 [label="MSTB #3";style=filled;fillcolor=palegreen;shape=oval]; 46*4882a593Smuzhiyun mstb4 [label="MSTB #4";style=filled;fillcolor=palegreen;shape=oval]; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun port1 [label="Port #1";shape=oval]; 49*4882a593Smuzhiyun port2 [label="Port #2";shape=oval]; 50*4882a593Smuzhiyun port3 [label="Port #3";shape=oval]; 51*4882a593Smuzhiyun port4 [label="Port #4";shape=oval]; 52*4882a593Smuzhiyun} 53