1*4882a593Smuzhiyun======================== 2*4882a593SmuzhiyunSoundWire Error Handling 3*4882a593Smuzhiyun======================== 4*4882a593Smuzhiyun 5*4882a593SmuzhiyunThe SoundWire PHY was designed with care and errors on the bus are going to 6*4882a593Smuzhiyunbe very unlikely, and if they happen it should be limited to single bit 7*4882a593Smuzhiyunerrors. Examples of this design can be found in the synchronization 8*4882a593Smuzhiyunmechanism (sync loss after two errors) and short CRCs used for the Bulk 9*4882a593SmuzhiyunRegister Access. 10*4882a593Smuzhiyun 11*4882a593SmuzhiyunThe errors can be detected with multiple mechanisms: 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun1. Bus clash or parity errors: This mechanism relies on low-level detectors 14*4882a593Smuzhiyun that are independent of the payload and usages, and they cover both control 15*4882a593Smuzhiyun and audio data. The current implementation only logs such errors. 16*4882a593Smuzhiyun Improvements could be invalidating an entire programming sequence and 17*4882a593Smuzhiyun restarting from a known position. In the case of such errors outside of a 18*4882a593Smuzhiyun control/command sequence, there is no concealment or recovery for audio 19*4882a593Smuzhiyun data enabled by the SoundWire protocol, the location of the error will also 20*4882a593Smuzhiyun impact its audibility (most-significant bits will be more impacted in PCM), 21*4882a593Smuzhiyun and after a number of such errors are detected the bus might be reset. Note 22*4882a593Smuzhiyun that bus clashes due to programming errors (two streams using the same bit 23*4882a593Smuzhiyun slots) or electrical issues during the transmit/receive transition cannot 24*4882a593Smuzhiyun be distinguished, although a recurring bus clash when audio is enabled is a 25*4882a593Smuzhiyun indication of a bus allocation issue. The interrupt mechanism can also help 26*4882a593Smuzhiyun identify Slaves which detected a Bus Clash or a Parity Error, but they may 27*4882a593Smuzhiyun not be responsible for the errors so resetting them individually is not a 28*4882a593Smuzhiyun viable recovery strategy. 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun2. Command status: Each command is associated with a status, which only 31*4882a593Smuzhiyun covers transmission of the data between devices. The ACK status indicates 32*4882a593Smuzhiyun that the command was received and will be executed by the end of the 33*4882a593Smuzhiyun current frame. A NAK indicates that the command was in error and will not 34*4882a593Smuzhiyun be applied. In case of a bad programming (command sent to non-existent 35*4882a593Smuzhiyun Slave or to a non-implemented register) or electrical issue, no response 36*4882a593Smuzhiyun signals the command was ignored. Some Master implementations allow for a 37*4882a593Smuzhiyun command to be retransmitted several times. If the retransmission fails, 38*4882a593Smuzhiyun backtracking and restarting the entire programming sequence might be a 39*4882a593Smuzhiyun solution. Alternatively some implementations might directly issue a bus 40*4882a593Smuzhiyun reset and re-enumerate all devices. 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun3. Timeouts: In a number of cases such as ChannelPrepare or 43*4882a593Smuzhiyun ClockStopPrepare, the bus driver is supposed to poll a register field until 44*4882a593Smuzhiyun it transitions to a NotFinished value of zero. The MIPI SoundWire spec 1.1 45*4882a593Smuzhiyun does not define timeouts but the MIPI SoundWire DisCo document adds 46*4882a593Smuzhiyun recommendation on timeouts. If such configurations do not complete, the 47*4882a593Smuzhiyun driver will return a -ETIMEOUT. Such timeouts are symptoms of a faulty 48*4882a593Smuzhiyun Slave device and are likely impossible to recover from. 49*4882a593Smuzhiyun 50*4882a593SmuzhiyunErrors during global reconfiguration sequences are extremely difficult to 51*4882a593Smuzhiyunhandle: 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun1. BankSwitch: An error during the last command issuing a BankSwitch is 54*4882a593Smuzhiyun difficult to backtrack from. Retransmitting the Bank Switch command may be 55*4882a593Smuzhiyun possible in a single segment setup, but this can lead to synchronization 56*4882a593Smuzhiyun problems when enabling multiple bus segments (a command with side effects 57*4882a593Smuzhiyun such as frame reconfiguration would be handled at different times). A global 58*4882a593Smuzhiyun hard-reset might be the best solution. 59*4882a593Smuzhiyun 60*4882a593SmuzhiyunNote that SoundWire does not provide a mechanism to detect illegal values 61*4882a593Smuzhiyunwritten in valid registers. In a number of cases the standard even mentions 62*4882a593Smuzhiyunthat the Slave might behave in implementation-defined ways. The bus 63*4882a593Smuzhiyunimplementation does not provide a recovery mechanism for such errors, Slave 64*4882a593Smuzhiyunor Master driver implementers are responsible for writing valid values in 65*4882a593Smuzhiyunvalid registers and implement additional range checking if needed. 66