1*4882a593Smuzhiyun.. SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe cx88 driver 4*4882a593Smuzhiyun=============== 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunAuthor: Gerd Hoffmann 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunDocumentation missing at the cx88 datasheet 9*4882a593Smuzhiyun------------------------------------------- 10*4882a593Smuzhiyun 11*4882a593SmuzhiyunMO_OUTPUT_FORMAT (0x310164) 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun.. code-block:: none 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun Previous default from DScaler: 0x1c1f0008 16*4882a593Smuzhiyun Digit 8: 31-28 17*4882a593Smuzhiyun 28: PREVREMOD = 1 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun Digit 7: 27-24 (0xc = 12 = b1100 ) 20*4882a593Smuzhiyun 27: COMBALT = 1 21*4882a593Smuzhiyun 26: PAL_INV_PHASE 22*4882a593Smuzhiyun (DScaler apparently set this to 1, resulted in sucky picture) 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun Digits 6,5: 23-16 25*4882a593Smuzhiyun 25-16: COMB_RANGE = 0x1f [default] (9 bits -> max 512) 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun Digit 4: 15-12 28*4882a593Smuzhiyun 15: DISIFX = 0 29*4882a593Smuzhiyun 14: INVCBF = 0 30*4882a593Smuzhiyun 13: DISADAPT = 0 31*4882a593Smuzhiyun 12: NARROWADAPT = 0 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun Digit 3: 11-8 34*4882a593Smuzhiyun 11: FORCE2H 35*4882a593Smuzhiyun 10: FORCEREMD 36*4882a593Smuzhiyun 9: NCHROMAEN 37*4882a593Smuzhiyun 8: NREMODEN 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun Digit 2: 7-4 40*4882a593Smuzhiyun 7-6: YCORE 41*4882a593Smuzhiyun 5-4: CCORE 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun Digit 1: 3-0 44*4882a593Smuzhiyun 3: RANGE = 1 45*4882a593Smuzhiyun 2: HACTEXT 46*4882a593Smuzhiyun 1: HSFMT 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun0x47 is the sync byte for MPEG-2 transport stream packets. 49*4882a593SmuzhiyunDatasheet incorrectly states to use 47 decimal. 188 is the length. 50*4882a593SmuzhiyunAll DVB compliant frontends output packets with this start code. 51*4882a593Smuzhiyun 52*4882a593SmuzhiyunHauppauge WinTV cx88 IR information 53*4882a593Smuzhiyun----------------------------------- 54*4882a593Smuzhiyun 55*4882a593SmuzhiyunThe controls for the mux are GPIO [0,1] for source, and GPIO 2 for muting. 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun====== ======== ================================================= 58*4882a593SmuzhiyunGPIO0 GPIO1 59*4882a593Smuzhiyun====== ======== ================================================= 60*4882a593Smuzhiyun 0 0 TV Audio 61*4882a593Smuzhiyun 1 0 FM radio 62*4882a593Smuzhiyun 0 1 Line-In 63*4882a593Smuzhiyun 1 1 Mono tuner bypass or CD passthru (tuner specific) 64*4882a593Smuzhiyun====== ======== ================================================= 65*4882a593Smuzhiyun 66*4882a593SmuzhiyunGPIO 16(I believe) is tied to the IR port (if present). 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun 69*4882a593SmuzhiyunFrom the data sheet: 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun- Register 24'h20004 PCI Interrupt Status 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun - bit [18] IR_SMP_INT Set when 32 input samples have been collected over 74*4882a593Smuzhiyun - gpio[16] pin into GP_SAMPLE register. 75*4882a593Smuzhiyun 76*4882a593SmuzhiyunWhat's missing from the data sheet: 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun- Setup 4KHz sampling rate (roughly 2x oversampled; good enough for our RC5 79*4882a593Smuzhiyun compat remote) 80*4882a593Smuzhiyun- set register 0x35C050 to 0xa80a80 81*4882a593Smuzhiyun- enable sampling 82*4882a593Smuzhiyun- set register 0x35C054 to 0x5 83*4882a593Smuzhiyun- enable the IRQ bit 18 in the interrupt mask register (and 84*4882a593Smuzhiyun provide for a handler) 85*4882a593Smuzhiyun 86*4882a593SmuzhiyunGP_SAMPLE register is at 0x35C058 87*4882a593Smuzhiyun 88*4882a593SmuzhiyunBits are then right shifted into the GP_SAMPLE register at the specified 89*4882a593Smuzhiyunrate; you get an interrupt when a full DWORD is received. 90*4882a593SmuzhiyunYou need to recover the actual RC5 bits out of the (oversampled) IR sensor 91*4882a593Smuzhiyunbits. (Hint: look for the 0/1and 1/0 crossings of the RC5 bi-phase data) An 92*4882a593Smuzhiyunactual raw RC5 code will span 2-3 DWORDS, depending on the actual alignment. 93*4882a593Smuzhiyun 94*4882a593SmuzhiyunI'm pretty sure when no IR signal is present the receiver is always in a 95*4882a593Smuzhiyunmarking state(1); but stray light, etc can cause intermittent noise values 96*4882a593Smuzhiyunas well. Remember, this is a free running sample of the IR receiver state 97*4882a593Smuzhiyunover time, so don't assume any sample starts at any particular place. 98*4882a593Smuzhiyun 99*4882a593SmuzhiyunAdditional info 100*4882a593Smuzhiyun~~~~~~~~~~~~~~~ 101*4882a593Smuzhiyun 102*4882a593SmuzhiyunThis data sheet (google search) seems to have a lovely description of the 103*4882a593SmuzhiyunRC5 basics: 104*4882a593Smuzhiyunhttp://www.atmel.com/dyn/resources/prod_documents/doc2817.pdf 105*4882a593Smuzhiyun 106*4882a593SmuzhiyunThis document has more data: 107*4882a593Smuzhiyunhttp://www.nenya.be/beor/electronics/rc5.htm 108*4882a593Smuzhiyun 109*4882a593SmuzhiyunThis document has a how to decode a bi-phase data stream: 110*4882a593Smuzhiyunhttp://www.ee.washington.edu/circuit_archive/text/ir_decode.txt 111*4882a593Smuzhiyun 112*4882a593SmuzhiyunThis document has still more info: 113*4882a593Smuzhiyunhttp://www.xs4all.nl/~sbp/knowledge/ir/rc5.htm 114