1*4882a593SmuzhiyunIntroduction 2*4882a593Smuzhiyun============ 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunThe FPGA subsystem supports reprogramming FPGAs dynamically under 5*4882a593SmuzhiyunLinux. Some of the core intentions of the FPGA subsystems are: 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun* The FPGA subsystem is vendor agnostic. 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun* The FPGA subsystem separates upper layers (userspace interfaces and 10*4882a593Smuzhiyun enumeration) from lower layers that know how to program a specific 11*4882a593Smuzhiyun FPGA. 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun* Code should not be shared between upper and lower layers. This 14*4882a593Smuzhiyun should go without saying. If that seems necessary, there's probably 15*4882a593Smuzhiyun framework functionality that can be added that will benefit 16*4882a593Smuzhiyun other users. Write the linux-fpga mailing list and maintainers and 17*4882a593Smuzhiyun seek out a solution that expands the framework for broad reuse. 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun* Generally, when adding code, think of the future. Plan for reuse. 20*4882a593Smuzhiyun 21*4882a593SmuzhiyunThe framework in the kernel is divided into: 22*4882a593Smuzhiyun 23*4882a593SmuzhiyunFPGA Manager 24*4882a593Smuzhiyun------------ 25*4882a593Smuzhiyun 26*4882a593SmuzhiyunIf you are adding a new FPGA or a new method of programming an FPGA, 27*4882a593Smuzhiyunthis is the subsystem for you. Low level FPGA manager drivers contain 28*4882a593Smuzhiyunthe knowledge of how to program a specific device. This subsystem 29*4882a593Smuzhiyunincludes the framework in fpga-mgr.c and the low level drivers that 30*4882a593Smuzhiyunare registered with it. 31*4882a593Smuzhiyun 32*4882a593SmuzhiyunFPGA Bridge 33*4882a593Smuzhiyun----------- 34*4882a593Smuzhiyun 35*4882a593SmuzhiyunFPGA Bridges prevent spurious signals from going out of an FPGA or a 36*4882a593Smuzhiyunregion of an FPGA during programming. They are disabled before 37*4882a593Smuzhiyunprogramming begins and re-enabled afterwards. An FPGA bridge may be 38*4882a593Smuzhiyunactual hard hardware that gates a bus to a CPU or a soft ("freeze") 39*4882a593Smuzhiyunbridge in FPGA fabric that surrounds a partial reconfiguration region 40*4882a593Smuzhiyunof an FPGA. This subsystem includes fpga-bridge.c and the low level 41*4882a593Smuzhiyundrivers that are registered with it. 42*4882a593Smuzhiyun 43*4882a593SmuzhiyunFPGA Region 44*4882a593Smuzhiyun----------- 45*4882a593Smuzhiyun 46*4882a593SmuzhiyunIf you are adding a new interface to the FPGA framework, add it on top 47*4882a593Smuzhiyunof an FPGA region. 48*4882a593Smuzhiyun 49*4882a593SmuzhiyunThe FPGA Region framework (fpga-region.c) associates managers and 50*4882a593Smuzhiyunbridges as reconfigurable regions. A region may refer to the whole 51*4882a593SmuzhiyunFPGA in full reconfiguration or to a partial reconfiguration region. 52*4882a593Smuzhiyun 53*4882a593SmuzhiyunThe Device Tree FPGA Region support (of-fpga-region.c) handles 54*4882a593Smuzhiyunreprogramming FPGAs when device tree overlays are applied. 55