1*4882a593Smuzhiyun======================== 2*4882a593SmuzhiyunThe Common Clk Framework 3*4882a593Smuzhiyun======================== 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun:Author: Mike Turquette <mturquette@ti.com> 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunThis document endeavours to explain the common clk framework details, 8*4882a593Smuzhiyunand how to port a platform over to this framework. It is not yet a 9*4882a593Smuzhiyundetailed explanation of the clock api in include/linux/clk.h, but 10*4882a593Smuzhiyunperhaps someday it will include that information. 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunIntroduction and interface split 13*4882a593Smuzhiyun================================ 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunThe common clk framework is an interface to control the clock nodes 16*4882a593Smuzhiyunavailable on various devices today. This may come in the form of clock 17*4882a593Smuzhiyungating, rate adjustment, muxing or other operations. This framework is 18*4882a593Smuzhiyunenabled with the CONFIG_COMMON_CLK option. 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunThe interface itself is divided into two halves, each shielded from the 21*4882a593Smuzhiyundetails of its counterpart. First is the common definition of struct 22*4882a593Smuzhiyunclk which unifies the framework-level accounting and infrastructure that 23*4882a593Smuzhiyunhas traditionally been duplicated across a variety of platforms. Second 24*4882a593Smuzhiyunis a common implementation of the clk.h api, defined in 25*4882a593Smuzhiyundrivers/clk/clk.c. Finally there is struct clk_ops, whose operations 26*4882a593Smuzhiyunare invoked by the clk api implementation. 27*4882a593Smuzhiyun 28*4882a593SmuzhiyunThe second half of the interface is comprised of the hardware-specific 29*4882a593Smuzhiyuncallbacks registered with struct clk_ops and the corresponding 30*4882a593Smuzhiyunhardware-specific structures needed to model a particular clock. For 31*4882a593Smuzhiyunthe remainder of this document any reference to a callback in struct 32*4882a593Smuzhiyunclk_ops, such as .enable or .set_rate, implies the hardware-specific 33*4882a593Smuzhiyunimplementation of that code. Likewise, references to struct clk_foo 34*4882a593Smuzhiyunserve as a convenient shorthand for the implementation of the 35*4882a593Smuzhiyunhardware-specific bits for the hypothetical "foo" hardware. 36*4882a593Smuzhiyun 37*4882a593SmuzhiyunTying the two halves of this interface together is struct clk_hw, which 38*4882a593Smuzhiyunis defined in struct clk_foo and pointed to within struct clk_core. This 39*4882a593Smuzhiyunallows for easy navigation between the two discrete halves of the common 40*4882a593Smuzhiyunclock interface. 41*4882a593Smuzhiyun 42*4882a593SmuzhiyunCommon data structures and api 43*4882a593Smuzhiyun============================== 44*4882a593Smuzhiyun 45*4882a593SmuzhiyunBelow is the common struct clk_core definition from 46*4882a593Smuzhiyundrivers/clk/clk.c, modified for brevity:: 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun struct clk_core { 49*4882a593Smuzhiyun const char *name; 50*4882a593Smuzhiyun const struct clk_ops *ops; 51*4882a593Smuzhiyun struct clk_hw *hw; 52*4882a593Smuzhiyun struct module *owner; 53*4882a593Smuzhiyun struct clk_core *parent; 54*4882a593Smuzhiyun const char **parent_names; 55*4882a593Smuzhiyun struct clk_core **parents; 56*4882a593Smuzhiyun u8 num_parents; 57*4882a593Smuzhiyun u8 new_parent_index; 58*4882a593Smuzhiyun ... 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun 61*4882a593SmuzhiyunThe members above make up the core of the clk tree topology. The clk 62*4882a593Smuzhiyunapi itself defines several driver-facing functions which operate on 63*4882a593Smuzhiyunstruct clk. That api is documented in include/linux/clk.h. 64*4882a593Smuzhiyun 65*4882a593SmuzhiyunPlatforms and devices utilizing the common struct clk_core use the struct 66*4882a593Smuzhiyunclk_ops pointer in struct clk_core to perform the hardware-specific parts of 67*4882a593Smuzhiyunthe operations defined in clk-provider.h:: 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun struct clk_ops { 70*4882a593Smuzhiyun int (*prepare)(struct clk_hw *hw); 71*4882a593Smuzhiyun void (*unprepare)(struct clk_hw *hw); 72*4882a593Smuzhiyun int (*is_prepared)(struct clk_hw *hw); 73*4882a593Smuzhiyun void (*unprepare_unused)(struct clk_hw *hw); 74*4882a593Smuzhiyun int (*enable)(struct clk_hw *hw); 75*4882a593Smuzhiyun void (*disable)(struct clk_hw *hw); 76*4882a593Smuzhiyun int (*is_enabled)(struct clk_hw *hw); 77*4882a593Smuzhiyun void (*disable_unused)(struct clk_hw *hw); 78*4882a593Smuzhiyun unsigned long (*recalc_rate)(struct clk_hw *hw, 79*4882a593Smuzhiyun unsigned long parent_rate); 80*4882a593Smuzhiyun long (*round_rate)(struct clk_hw *hw, 81*4882a593Smuzhiyun unsigned long rate, 82*4882a593Smuzhiyun unsigned long *parent_rate); 83*4882a593Smuzhiyun int (*determine_rate)(struct clk_hw *hw, 84*4882a593Smuzhiyun struct clk_rate_request *req); 85*4882a593Smuzhiyun int (*set_parent)(struct clk_hw *hw, u8 index); 86*4882a593Smuzhiyun u8 (*get_parent)(struct clk_hw *hw); 87*4882a593Smuzhiyun int (*set_rate)(struct clk_hw *hw, 88*4882a593Smuzhiyun unsigned long rate, 89*4882a593Smuzhiyun unsigned long parent_rate); 90*4882a593Smuzhiyun int (*set_rate_and_parent)(struct clk_hw *hw, 91*4882a593Smuzhiyun unsigned long rate, 92*4882a593Smuzhiyun unsigned long parent_rate, 93*4882a593Smuzhiyun u8 index); 94*4882a593Smuzhiyun unsigned long (*recalc_accuracy)(struct clk_hw *hw, 95*4882a593Smuzhiyun unsigned long parent_accuracy); 96*4882a593Smuzhiyun int (*get_phase)(struct clk_hw *hw); 97*4882a593Smuzhiyun int (*set_phase)(struct clk_hw *hw, int degrees); 98*4882a593Smuzhiyun void (*init)(struct clk_hw *hw); 99*4882a593Smuzhiyun void (*debug_init)(struct clk_hw *hw, 100*4882a593Smuzhiyun struct dentry *dentry); 101*4882a593Smuzhiyun }; 102*4882a593Smuzhiyun 103*4882a593SmuzhiyunHardware clk implementations 104*4882a593Smuzhiyun============================ 105*4882a593Smuzhiyun 106*4882a593SmuzhiyunThe strength of the common struct clk_core comes from its .ops and .hw pointers 107*4882a593Smuzhiyunwhich abstract the details of struct clk from the hardware-specific bits, and 108*4882a593Smuzhiyunvice versa. To illustrate consider the simple gateable clk implementation in 109*4882a593Smuzhiyundrivers/clk/clk-gate.c:: 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun struct clk_gate { 112*4882a593Smuzhiyun struct clk_hw hw; 113*4882a593Smuzhiyun void __iomem *reg; 114*4882a593Smuzhiyun u8 bit_idx; 115*4882a593Smuzhiyun ... 116*4882a593Smuzhiyun }; 117*4882a593Smuzhiyun 118*4882a593Smuzhiyunstruct clk_gate contains struct clk_hw hw as well as hardware-specific 119*4882a593Smuzhiyunknowledge about which register and bit controls this clk's gating. 120*4882a593SmuzhiyunNothing about clock topology or accounting, such as enable_count or 121*4882a593Smuzhiyunnotifier_count, is needed here. That is all handled by the common 122*4882a593Smuzhiyunframework code and struct clk_core. 123*4882a593Smuzhiyun 124*4882a593SmuzhiyunLet's walk through enabling this clk from driver code:: 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun struct clk *clk; 127*4882a593Smuzhiyun clk = clk_get(NULL, "my_gateable_clk"); 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun clk_prepare(clk); 130*4882a593Smuzhiyun clk_enable(clk); 131*4882a593Smuzhiyun 132*4882a593SmuzhiyunThe call graph for clk_enable is very simple:: 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun clk_enable(clk); 135*4882a593Smuzhiyun clk->ops->enable(clk->hw); 136*4882a593Smuzhiyun [resolves to...] 137*4882a593Smuzhiyun clk_gate_enable(hw); 138*4882a593Smuzhiyun [resolves struct clk gate with to_clk_gate(hw)] 139*4882a593Smuzhiyun clk_gate_set_bit(gate); 140*4882a593Smuzhiyun 141*4882a593SmuzhiyunAnd the definition of clk_gate_set_bit:: 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun static void clk_gate_set_bit(struct clk_gate *gate) 144*4882a593Smuzhiyun { 145*4882a593Smuzhiyun u32 reg; 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun reg = __raw_readl(gate->reg); 148*4882a593Smuzhiyun reg |= BIT(gate->bit_idx); 149*4882a593Smuzhiyun writel(reg, gate->reg); 150*4882a593Smuzhiyun } 151*4882a593Smuzhiyun 152*4882a593SmuzhiyunNote that to_clk_gate is defined as:: 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw) 155*4882a593Smuzhiyun 156*4882a593SmuzhiyunThis pattern of abstraction is used for every clock hardware 157*4882a593Smuzhiyunrepresentation. 158*4882a593Smuzhiyun 159*4882a593SmuzhiyunSupporting your own clk hardware 160*4882a593Smuzhiyun================================ 161*4882a593Smuzhiyun 162*4882a593SmuzhiyunWhen implementing support for a new type of clock it is only necessary to 163*4882a593Smuzhiyuninclude the following header:: 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun #include <linux/clk-provider.h> 166*4882a593Smuzhiyun 167*4882a593SmuzhiyunTo construct a clk hardware structure for your platform you must define 168*4882a593Smuzhiyunthe following:: 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun struct clk_foo { 171*4882a593Smuzhiyun struct clk_hw hw; 172*4882a593Smuzhiyun ... hardware specific data goes here ... 173*4882a593Smuzhiyun }; 174*4882a593Smuzhiyun 175*4882a593SmuzhiyunTo take advantage of your data you'll need to support valid operations 176*4882a593Smuzhiyunfor your clk:: 177*4882a593Smuzhiyun 178*4882a593Smuzhiyun struct clk_ops clk_foo_ops = { 179*4882a593Smuzhiyun .enable = &clk_foo_enable, 180*4882a593Smuzhiyun .disable = &clk_foo_disable, 181*4882a593Smuzhiyun }; 182*4882a593Smuzhiyun 183*4882a593SmuzhiyunImplement the above functions using container_of:: 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun #define to_clk_foo(_hw) container_of(_hw, struct clk_foo, hw) 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun int clk_foo_enable(struct clk_hw *hw) 188*4882a593Smuzhiyun { 189*4882a593Smuzhiyun struct clk_foo *foo; 190*4882a593Smuzhiyun 191*4882a593Smuzhiyun foo = to_clk_foo(hw); 192*4882a593Smuzhiyun 193*4882a593Smuzhiyun ... perform magic on foo ... 194*4882a593Smuzhiyun 195*4882a593Smuzhiyun return 0; 196*4882a593Smuzhiyun }; 197*4882a593Smuzhiyun 198*4882a593SmuzhiyunBelow is a matrix detailing which clk_ops are mandatory based upon the 199*4882a593Smuzhiyunhardware capabilities of that clock. A cell marked as "y" means 200*4882a593Smuzhiyunmandatory, a cell marked as "n" implies that either including that 201*4882a593Smuzhiyuncallback is invalid or otherwise unnecessary. Empty cells are either 202*4882a593Smuzhiyunoptional or must be evaluated on a case-by-case basis. 203*4882a593Smuzhiyun 204*4882a593Smuzhiyun.. table:: clock hardware characteristics 205*4882a593Smuzhiyun 206*4882a593Smuzhiyun +----------------+------+-------------+---------------+-------------+------+ 207*4882a593Smuzhiyun | | gate | change rate | single parent | multiplexer | root | 208*4882a593Smuzhiyun +================+======+=============+===============+=============+======+ 209*4882a593Smuzhiyun |.prepare | | | | | | 210*4882a593Smuzhiyun +----------------+------+-------------+---------------+-------------+------+ 211*4882a593Smuzhiyun |.unprepare | | | | | | 212*4882a593Smuzhiyun +----------------+------+-------------+---------------+-------------+------+ 213*4882a593Smuzhiyun +----------------+------+-------------+---------------+-------------+------+ 214*4882a593Smuzhiyun |.enable | y | | | | | 215*4882a593Smuzhiyun +----------------+------+-------------+---------------+-------------+------+ 216*4882a593Smuzhiyun |.disable | y | | | | | 217*4882a593Smuzhiyun +----------------+------+-------------+---------------+-------------+------+ 218*4882a593Smuzhiyun |.is_enabled | y | | | | | 219*4882a593Smuzhiyun +----------------+------+-------------+---------------+-------------+------+ 220*4882a593Smuzhiyun +----------------+------+-------------+---------------+-------------+------+ 221*4882a593Smuzhiyun |.recalc_rate | | y | | | | 222*4882a593Smuzhiyun +----------------+------+-------------+---------------+-------------+------+ 223*4882a593Smuzhiyun |.round_rate | | y [1]_ | | | | 224*4882a593Smuzhiyun +----------------+------+-------------+---------------+-------------+------+ 225*4882a593Smuzhiyun |.determine_rate | | y [1]_ | | | | 226*4882a593Smuzhiyun +----------------+------+-------------+---------------+-------------+------+ 227*4882a593Smuzhiyun |.set_rate | | y | | | | 228*4882a593Smuzhiyun +----------------+------+-------------+---------------+-------------+------+ 229*4882a593Smuzhiyun +----------------+------+-------------+---------------+-------------+------+ 230*4882a593Smuzhiyun |.set_parent | | | n | y | n | 231*4882a593Smuzhiyun +----------------+------+-------------+---------------+-------------+------+ 232*4882a593Smuzhiyun |.get_parent | | | n | y | n | 233*4882a593Smuzhiyun +----------------+------+-------------+---------------+-------------+------+ 234*4882a593Smuzhiyun +----------------+------+-------------+---------------+-------------+------+ 235*4882a593Smuzhiyun |.recalc_accuracy| | | | | | 236*4882a593Smuzhiyun +----------------+------+-------------+---------------+-------------+------+ 237*4882a593Smuzhiyun +----------------+------+-------------+---------------+-------------+------+ 238*4882a593Smuzhiyun |.init | | | | | | 239*4882a593Smuzhiyun +----------------+------+-------------+---------------+-------------+------+ 240*4882a593Smuzhiyun 241*4882a593Smuzhiyun.. [1] either one of round_rate or determine_rate is required. 242*4882a593Smuzhiyun 243*4882a593SmuzhiyunFinally, register your clock at run-time with a hardware-specific 244*4882a593Smuzhiyunregistration function. This function simply populates struct clk_foo's 245*4882a593Smuzhiyundata and then passes the common struct clk parameters to the framework 246*4882a593Smuzhiyunwith a call to:: 247*4882a593Smuzhiyun 248*4882a593Smuzhiyun clk_register(...) 249*4882a593Smuzhiyun 250*4882a593SmuzhiyunSee the basic clock types in ``drivers/clk/clk-*.c`` for examples. 251*4882a593Smuzhiyun 252*4882a593SmuzhiyunDisabling clock gating of unused clocks 253*4882a593Smuzhiyun======================================= 254*4882a593Smuzhiyun 255*4882a593SmuzhiyunSometimes during development it can be useful to be able to bypass the 256*4882a593Smuzhiyundefault disabling of unused clocks. For example, if drivers aren't enabling 257*4882a593Smuzhiyunclocks properly but rely on them being on from the bootloader, bypassing 258*4882a593Smuzhiyunthe disabling means that the driver will remain functional while the issues 259*4882a593Smuzhiyunare sorted out. 260*4882a593Smuzhiyun 261*4882a593SmuzhiyunTo bypass this disabling, include "clk_ignore_unused" in the bootargs to the 262*4882a593Smuzhiyunkernel. 263*4882a593Smuzhiyun 264*4882a593SmuzhiyunLocking 265*4882a593Smuzhiyun======= 266*4882a593Smuzhiyun 267*4882a593SmuzhiyunThe common clock framework uses two global locks, the prepare lock and the 268*4882a593Smuzhiyunenable lock. 269*4882a593Smuzhiyun 270*4882a593SmuzhiyunThe enable lock is a spinlock and is held across calls to the .enable, 271*4882a593Smuzhiyun.disable operations. Those operations are thus not allowed to sleep, 272*4882a593Smuzhiyunand calls to the clk_enable(), clk_disable() API functions are allowed in 273*4882a593Smuzhiyunatomic context. 274*4882a593Smuzhiyun 275*4882a593SmuzhiyunFor clk_is_enabled() API, it is also designed to be allowed to be used in 276*4882a593Smuzhiyunatomic context. However, it doesn't really make any sense to hold the enable 277*4882a593Smuzhiyunlock in core, unless you want to do something else with the information of 278*4882a593Smuzhiyunthe enable state with that lock held. Otherwise, seeing if a clk is enabled is 279*4882a593Smuzhiyuna one-shot read of the enabled state, which could just as easily change after 280*4882a593Smuzhiyunthe function returns because the lock is released. Thus the user of this API 281*4882a593Smuzhiyunneeds to handle synchronizing the read of the state with whatever they're 282*4882a593Smuzhiyunusing it for to make sure that the enable state doesn't change during that 283*4882a593Smuzhiyuntime. 284*4882a593Smuzhiyun 285*4882a593SmuzhiyunThe prepare lock is a mutex and is held across calls to all other operations. 286*4882a593SmuzhiyunAll those operations are allowed to sleep, and calls to the corresponding API 287*4882a593Smuzhiyunfunctions are not allowed in atomic context. 288*4882a593Smuzhiyun 289*4882a593SmuzhiyunThis effectively divides operations in two groups from a locking perspective. 290*4882a593Smuzhiyun 291*4882a593SmuzhiyunDrivers don't need to manually protect resources shared between the operations 292*4882a593Smuzhiyunof one group, regardless of whether those resources are shared by multiple 293*4882a593Smuzhiyunclocks or not. However, access to resources that are shared between operations 294*4882a593Smuzhiyunof the two groups needs to be protected by the drivers. An example of such a 295*4882a593Smuzhiyunresource would be a register that controls both the clock rate and the clock 296*4882a593Smuzhiyunenable/disable state. 297*4882a593Smuzhiyun 298*4882a593SmuzhiyunThe clock framework is reentrant, in that a driver is allowed to call clock 299*4882a593Smuzhiyunframework functions from within its implementation of clock operations. This 300*4882a593Smuzhiyuncan for instance cause a .set_rate operation of one clock being called from 301*4882a593Smuzhiyunwithin the .set_rate operation of another clock. This case must be considered 302*4882a593Smuzhiyunin the driver implementations, but the code flow is usually controlled by the 303*4882a593Smuzhiyundriver in that case. 304*4882a593Smuzhiyun 305*4882a593SmuzhiyunNote that locking must also be considered when code outside of the common 306*4882a593Smuzhiyunclock framework needs to access resources used by the clock operations. This 307*4882a593Smuzhiyunis considered out of scope of this document. 308