1*4882a593SmuzhiyunZTE zx2967 Watchdog timer 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun- compatible : should be one of the following. 6*4882a593Smuzhiyun * zte,zx296718-wdt 7*4882a593Smuzhiyun- reg : Specifies base physical address and size of the registers. 8*4882a593Smuzhiyun- clocks : Pairs of phandle and specifier referencing the controller's clocks. 9*4882a593Smuzhiyun- resets : Reference to the reset controller controlling the watchdog 10*4882a593Smuzhiyun controller. 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunOptional properties: 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun- timeout-sec : Contains the watchdog timeout in seconds. 15*4882a593Smuzhiyun- zte,wdt-reset-sysctrl : Directs how to reset system by the watchdog. 16*4882a593Smuzhiyun if we don't want to restart system when watchdog been triggered, 17*4882a593Smuzhiyun it's not required, vice versa. 18*4882a593Smuzhiyun It should include following fields. 19*4882a593Smuzhiyun * phandle of aon-sysctrl. 20*4882a593Smuzhiyun * offset of register that be written, should be 0xb0. 21*4882a593Smuzhiyun * configure value that be written to aon-sysctrl. 22*4882a593Smuzhiyun * bit mask, corresponding bits will be affected. 23*4882a593Smuzhiyun 24*4882a593SmuzhiyunExample: 25*4882a593Smuzhiyun 26*4882a593Smuzhiyunwdt: watchdog@1465000 { 27*4882a593Smuzhiyun compatible = "zte,zx296718-wdt"; 28*4882a593Smuzhiyun reg = <0x1465000 0x1000>; 29*4882a593Smuzhiyun clocks = <&topcrm WDT_WCLK>; 30*4882a593Smuzhiyun resets = <&toprst 35>; 31*4882a593Smuzhiyun zte,wdt-reset-sysctrl = <&aon_sysctrl 0xb0 1 0x115>; 32*4882a593Smuzhiyun}; 33