1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/watchdog/snps,dw-wdt.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Synopsys Designware Watchdog Timer 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunallOf: 10*4882a593Smuzhiyun - $ref: "watchdog.yaml#" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyunmaintainers: 13*4882a593Smuzhiyun - Jamie Iles <jamie@jamieiles.com> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyunproperties: 16*4882a593Smuzhiyun compatible: 17*4882a593Smuzhiyun const: snps,dw-wdt 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun reg: 20*4882a593Smuzhiyun maxItems: 1 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun interrupts: 23*4882a593Smuzhiyun description: DW Watchdog pre-timeout interrupt 24*4882a593Smuzhiyun maxItems: 1 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun clocks: 27*4882a593Smuzhiyun minItems: 1 28*4882a593Smuzhiyun items: 29*4882a593Smuzhiyun - description: Watchdog timer reference clock 30*4882a593Smuzhiyun - description: APB3 interface clock 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun clock-names: 33*4882a593Smuzhiyun minItems: 1 34*4882a593Smuzhiyun items: 35*4882a593Smuzhiyun - const: tclk 36*4882a593Smuzhiyun - const: pclk 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun resets: 39*4882a593Smuzhiyun description: Phandle to the DW Watchdog reset lane 40*4882a593Smuzhiyun maxItems: 1 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun snps,watchdog-tops: 43*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/uint32-array 44*4882a593Smuzhiyun description: | 45*4882a593Smuzhiyun DW APB Watchdog custom timer intervals - Timeout Period ranges (TOPs). 46*4882a593Smuzhiyun Each TOP is a number loaded into the watchdog counter at the moment of 47*4882a593Smuzhiyun the timer restart. The counter decrementing happens each tick of the 48*4882a593Smuzhiyun reference clock. Therefore the TOPs array is equivalent to an array of 49*4882a593Smuzhiyun the timer expiration intervals supported by the DW APB Watchdog. Note 50*4882a593Smuzhiyun DW APB Watchdog IP-core might be synthesized with fixed TOP values, 51*4882a593Smuzhiyun in which case this property is unnecessary with default TOPs utilized. 52*4882a593Smuzhiyun default: [0x0001000 0x0002000 0x0004000 0x0008000 53*4882a593Smuzhiyun 0x0010000 0x0020000 0x0040000 0x0080000 54*4882a593Smuzhiyun 0x0100000 0x0200000 0x0400000 0x0800000 55*4882a593Smuzhiyun 0x1000000 0x2000000 0x4000000 0x8000000] 56*4882a593Smuzhiyun minItems: 16 57*4882a593Smuzhiyun maxItems: 16 58*4882a593Smuzhiyun 59*4882a593SmuzhiyununevaluatedProperties: false 60*4882a593Smuzhiyun 61*4882a593Smuzhiyunrequired: 62*4882a593Smuzhiyun - compatible 63*4882a593Smuzhiyun - reg 64*4882a593Smuzhiyun - clocks 65*4882a593Smuzhiyun 66*4882a593Smuzhiyunexamples: 67*4882a593Smuzhiyun - | 68*4882a593Smuzhiyun watchdog@ffd02000 { 69*4882a593Smuzhiyun compatible = "snps,dw-wdt"; 70*4882a593Smuzhiyun reg = <0xffd02000 0x1000>; 71*4882a593Smuzhiyun interrupts = <0 171 4>; 72*4882a593Smuzhiyun clocks = <&per_base_clk>; 73*4882a593Smuzhiyun resets = <&wdt_rst>; 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun - | 77*4882a593Smuzhiyun watchdog@ffd02000 { 78*4882a593Smuzhiyun compatible = "snps,dw-wdt"; 79*4882a593Smuzhiyun reg = <0xffd02000 0x1000>; 80*4882a593Smuzhiyun interrupts = <0 171 4>; 81*4882a593Smuzhiyun clocks = <&per_base_clk>; 82*4882a593Smuzhiyun clock-names = "tclk"; 83*4882a593Smuzhiyun snps,watchdog-tops = <0x000000FF 0x000001FF 0x000003FF 84*4882a593Smuzhiyun 0x000007FF 0x0000FFFF 0x0001FFFF 85*4882a593Smuzhiyun 0x0003FFFF 0x0007FFFF 0x000FFFFF 86*4882a593Smuzhiyun 0x001FFFFF 0x003FFFFF 0x007FFFFF 87*4882a593Smuzhiyun 0x00FFFFFF 0x01FFFFFF 0x03FFFFFF 88*4882a593Smuzhiyun 0x07FFFFFF>; 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun... 91