1*4882a593SmuzhiyunMediatek SoCs Watchdog timer 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun- compatible should contain: 6*4882a593Smuzhiyun "mediatek,mt2701-wdt", "mediatek,mt6589-wdt": for MT2701 7*4882a593Smuzhiyun "mediatek,mt2712-wdt", "mediatek,mt6589-wdt": for MT2712 8*4882a593Smuzhiyun "mediatek,mt6589-wdt": for MT6589 9*4882a593Smuzhiyun "mediatek,mt6797-wdt", "mediatek,mt6589-wdt": for MT6797 10*4882a593Smuzhiyun "mediatek,mt7622-wdt", "mediatek,mt6589-wdt": for MT7622 11*4882a593Smuzhiyun "mediatek,mt7623-wdt", "mediatek,mt6589-wdt": for MT7623 12*4882a593Smuzhiyun "mediatek,mt7629-wdt", "mediatek,mt6589-wdt": for MT7629 13*4882a593Smuzhiyun "mediatek,mt8183-wdt", "mediatek,mt6589-wdt": for MT8183 14*4882a593Smuzhiyun "mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun- reg : Specifies base physical address and size of the registers. 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunOptional properties: 19*4882a593Smuzhiyun- timeout-sec: contains the watchdog timeout in seconds. 20*4882a593Smuzhiyun- #reset-cells: Should be 1. 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunExample: 23*4882a593Smuzhiyun 24*4882a593Smuzhiyunwatchdog: watchdog@10007000 { 25*4882a593Smuzhiyun compatible = "mediatek,mt8183-wdt", 26*4882a593Smuzhiyun "mediatek,mt6589-wdt"; 27*4882a593Smuzhiyun reg = <0 0x10007000 0 0x100>; 28*4882a593Smuzhiyun timeout-sec = <10>; 29*4882a593Smuzhiyun #reset-cells = <1>; 30*4882a593Smuzhiyun}; 31