1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/watchdog/fsl-imx-wdt.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Freescale i.MX Watchdog Timer (WDT) Controller 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Anson Huang <Anson.Huang@nxp.com> 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunallOf: 13*4882a593Smuzhiyun - $ref: "watchdog.yaml#" 14*4882a593Smuzhiyun 15*4882a593Smuzhiyunproperties: 16*4882a593Smuzhiyun compatible: 17*4882a593Smuzhiyun oneOf: 18*4882a593Smuzhiyun - const: fsl,imx21-wdt 19*4882a593Smuzhiyun - items: 20*4882a593Smuzhiyun - enum: 21*4882a593Smuzhiyun - fsl,imx8mm-wdt 22*4882a593Smuzhiyun - fsl,imx8mn-wdt 23*4882a593Smuzhiyun - fsl,imx8mp-wdt 24*4882a593Smuzhiyun - fsl,imx8mq-wdt 25*4882a593Smuzhiyun - const: fsl,imx21-wdt 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun reg: 28*4882a593Smuzhiyun maxItems: 1 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun interrupts: 31*4882a593Smuzhiyun maxItems: 1 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun clocks: 34*4882a593Smuzhiyun maxItems: 1 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun fsl,ext-reset-output: 37*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/flag 38*4882a593Smuzhiyun description: | 39*4882a593Smuzhiyun If present, the watchdog device is configured to assert its 40*4882a593Smuzhiyun external reset (WDOG_B) instead of issuing a software reset. 41*4882a593Smuzhiyun 42*4882a593Smuzhiyunrequired: 43*4882a593Smuzhiyun - compatible 44*4882a593Smuzhiyun - interrupts 45*4882a593Smuzhiyun - reg 46*4882a593Smuzhiyun 47*4882a593SmuzhiyununevaluatedProperties: false 48*4882a593Smuzhiyun 49*4882a593Smuzhiyunexamples: 50*4882a593Smuzhiyun - | 51*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/arm-gic.h> 52*4882a593Smuzhiyun #include <dt-bindings/clock/imx6qdl-clock.h> 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun watchdog@20bc000 { 55*4882a593Smuzhiyun compatible = "fsl,imx21-wdt"; 56*4882a593Smuzhiyun reg = <0x020bc000 0x4000>; 57*4882a593Smuzhiyun interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; 58*4882a593Smuzhiyun clocks = <&clks IMX6QDL_CLK_IPG>; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun... 62