1*4882a593Smuzhiyun* Atmel SAMA5D4 Watchdog Timer (WDT) Controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: "atmel,sama5d4-wdt" or "microchip,sam9x60-wdt" 5*4882a593Smuzhiyun- reg: base physical address and length of memory mapped region. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunOptional properties: 8*4882a593Smuzhiyun- timeout-sec: watchdog timeout value (in seconds). 9*4882a593Smuzhiyun- interrupts: interrupt number to the CPU. 10*4882a593Smuzhiyun- atmel,watchdog-type: should be "hardware" or "software". 11*4882a593Smuzhiyun "hardware": enable watchdog fault reset. A watchdog fault triggers 12*4882a593Smuzhiyun watchdog reset. 13*4882a593Smuzhiyun "software": enable watchdog fault interrupt. A watchdog fault asserts 14*4882a593Smuzhiyun watchdog interrupt. 15*4882a593Smuzhiyun- atmel,idle-halt: present if you want to stop the watchdog when the CPU is 16*4882a593Smuzhiyun in idle state. 17*4882a593Smuzhiyun CAUTION: This property should be used with care, it actually makes the 18*4882a593Smuzhiyun watchdog not counting when the CPU is in idle state, therefore the 19*4882a593Smuzhiyun watchdog reset time depends on mean CPU usage and will not reset at all 20*4882a593Smuzhiyun if the CPU stop working while it is in idle state, which is probably 21*4882a593Smuzhiyun not what you want. 22*4882a593Smuzhiyun- atmel,dbg-halt: present if you want to stop the watchdog when the CPU is 23*4882a593Smuzhiyun in debug state. 24*4882a593Smuzhiyun 25*4882a593SmuzhiyunExample: 26*4882a593Smuzhiyun watchdog@fc068640 { 27*4882a593Smuzhiyun compatible = "atmel,sama5d4-wdt"; 28*4882a593Smuzhiyun reg = <0xfc068640 0x10>; 29*4882a593Smuzhiyun interrupts = <4 IRQ_TYPE_LEVEL_HIGH 5>; 30*4882a593Smuzhiyun timeout-sec = <10>; 31*4882a593Smuzhiyun atmel,watchdog-type = "hardware"; 32*4882a593Smuzhiyun atmel,dbg-halt; 33*4882a593Smuzhiyun atmel,idle-halt; 34*4882a593Smuzhiyun }; 35