1*4882a593Smuzhiyun* virtio IOMMU PCI device 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunWhen virtio-iommu uses the PCI transport, its programming interface is 4*4882a593Smuzhiyundiscovered dynamically by the PCI probing infrastructure. However the 5*4882a593Smuzhiyundevice tree statically describes the relation between IOMMU and DMA 6*4882a593Smuzhiyunmasters. Therefore, the PCI root complex that hosts the virtio-iommu 7*4882a593Smuzhiyuncontains a child node representing the IOMMU device explicitly. 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunRequired properties: 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun- compatible: Should be "virtio,pci-iommu" 12*4882a593Smuzhiyun- reg: PCI address of the IOMMU. As defined in the PCI Bus 13*4882a593Smuzhiyun Binding reference [1], the reg property is a five-cell 14*4882a593Smuzhiyun address encoded as (phys.hi phys.mid phys.lo size.hi 15*4882a593Smuzhiyun size.lo). phys.hi should contain the device's BDF as 16*4882a593Smuzhiyun 0b00000000 bbbbbbbb dddddfff 00000000. The other cells 17*4882a593Smuzhiyun should be zero. 18*4882a593Smuzhiyun- #iommu-cells: Each platform DMA master managed by the IOMMU is assigned 19*4882a593Smuzhiyun an endpoint ID, described by the "iommus" property [2]. 20*4882a593Smuzhiyun For virtio-iommu, #iommu-cells must be 1. 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunNotes: 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun- DMA from the IOMMU device isn't managed by another IOMMU. Therefore the 25*4882a593Smuzhiyun virtio-iommu node doesn't have an "iommus" property, and is omitted from 26*4882a593Smuzhiyun the iommu-map property of the root complex. 27*4882a593Smuzhiyun 28*4882a593SmuzhiyunExample: 29*4882a593Smuzhiyun 30*4882a593Smuzhiyunpcie@10000000 { 31*4882a593Smuzhiyun compatible = "pci-host-ecam-generic"; 32*4882a593Smuzhiyun ... 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* The IOMMU programming interface uses slot 00:01.0 */ 35*4882a593Smuzhiyun iommu0: iommu@0008 { 36*4882a593Smuzhiyun compatible = "virtio,pci-iommu"; 37*4882a593Smuzhiyun reg = <0x00000800 0 0 0 0>; 38*4882a593Smuzhiyun #iommu-cells = <1>; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* 42*4882a593Smuzhiyun * The IOMMU manages all functions in this PCI domain except 43*4882a593Smuzhiyun * itself. Omit BDF 00:01.0. 44*4882a593Smuzhiyun */ 45*4882a593Smuzhiyun iommu-map = <0x0 &iommu0 0x0 0x8> 46*4882a593Smuzhiyun <0x9 &iommu0 0x9 0xfff7>; 47*4882a593Smuzhiyun}; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyunpcie@20000000 { 50*4882a593Smuzhiyun compatible = "pci-host-ecam-generic"; 51*4882a593Smuzhiyun ... 52*4882a593Smuzhiyun /* 53*4882a593Smuzhiyun * The IOMMU also manages all functions from this domain, 54*4882a593Smuzhiyun * with endpoint IDs 0x10000 - 0x1ffff 55*4882a593Smuzhiyun */ 56*4882a593Smuzhiyun iommu-map = <0x0 &iommu0 0x10000 0x10000>; 57*4882a593Smuzhiyun}; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyunethernet@fe001000 { 60*4882a593Smuzhiyun ... 61*4882a593Smuzhiyun /* The IOMMU manages this platform device with endpoint ID 0x20000 */ 62*4882a593Smuzhiyun iommus = <&iommu0 0x20000>; 63*4882a593Smuzhiyun}; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun[1] Documentation/devicetree/bindings/pci/pci.txt 66*4882a593Smuzhiyun[2] Documentation/devicetree/bindings/iommu/iommu.txt 67