1*4882a593SmuzhiyunThe Rockchip display port interface should be configured based on 2*4882a593Smuzhiyunthe type of panel connected to it. 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunRequired properties: 5*4882a593Smuzhiyun- compatible: value should be "rockchip,rk32-lvds". 6*4882a593Smuzhiyun- reg: physical base address and length of the LVDS registers set. 7*4882a593Smuzhiyun- interrupts: interrupt number to the cpu and interrupt proterties. 8*4882a593Smuzhiyun- clocks: must include clock specifiers corresponding to entries in the 9*4882a593Smuzhiyun clock-names property. 10*4882a593Smuzhiyun- clock-names: list of clock names sorted in the same order as the clocks 11*4882a593Smuzhiyun property.. 12*4882a593Smuzhiyun 13*4882a593SmuzhiyunExample: 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunSoC specific DT entry: 16*4882a593Smuzhiyun lvds: lvds@ff96c000 { 17*4882a593Smuzhiyun compatible = "rockchip,rk32-lvds"; 18*4882a593Smuzhiyun reg = <0xff96c000 0x4000>; 19*4882a593Smuzhiyun clocks = <&clk_gates16 7>; 20*4882a593Smuzhiyun clock-names = "pclk_lvds"; 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun 23