1*4882a593SmuzhiyunDevice-Tree bindings for Rockchip Video Codec. 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: There are several vcodec IP inside rockchip chips. 5*4882a593Smuzhiyun Decoder should be one of following: 6*4882a593Smuzhiyun "rockchip,vpu-decoder-v1", 7*4882a593Smuzhiyun "rockchip,avs-plus-decoder", 8*4882a593Smuzhiyun "rockchip,vpu-decoder-v2", 9*4882a593Smuzhiyun "rockchip,vpu-decoder-px30", 10*4882a593Smuzhiyun "rockchip,vpu-decoder-rk3288", 11*4882a593Smuzhiyun "rockchip,vpu-decoder-rk3368", 12*4882a593Smuzhiyun "rockchip,hevc-decoder", 13*4882a593Smuzhiyun "rockchip,hevc-decoder-px30", 14*4882a593Smuzhiyun "rockchip,hevc-decoder-rk3368", 15*4882a593Smuzhiyun "rockchip,rkv-decoder-v1", 16*4882a593Smuzhiyun "rockchip,rkv-decoder-v2", 17*4882a593Smuzhiyun "rockchip,rkv-decoder-rk3399", 18*4882a593Smuzhiyun "rockchip,rkv-decoder-rk3328", 19*4882a593Smuzhiyun "rockchip,rkv-jpeg-decoder-v1", 20*4882a593Smuzhiyun Encoder should be one of following: 21*4882a593Smuzhiyun "rockchip,vpu-encoder-v1", 22*4882a593Smuzhiyun "rockchip,vpu-encoder-v2", 23*4882a593Smuzhiyun "rockchip,vpu-encoder-px30", 24*4882a593Smuzhiyun "rockchip,rkv-encoder-v1", 25*4882a593Smuzhiyun "rockchip,rkv-encoder-v2", 26*4882a593Smuzhiyun "rockchip,rkv-encoder-rv1108", 27*4882a593Smuzhiyun "rockchip,hevc-encoder-v22", 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun- rockchip,srv: The pointer of service device node. 30*4882a593Smuzhiyun the value must be the name of service device, like <&mpp_srv>. 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun- rockchip,taskqueue-node: The taskqueue node number of current device working. 33*4882a593Smuzhiyun the value must between 0 and rockchip,taskqueue-count 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun- rockchip,resetgroup-node: The resetgroup node number of current reset group. 36*4882a593Smuzhiyun If two devices have the same reset clk, they should in the same reset group. 37*4882a593Smuzhiyun the value must between 0 and rockchip,resetgroup-count 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun- reset-name: The name of reset clk. 40*4882a593Smuzhiyun If two devices have the same reset clk, the reset-name should stay the same 41*4882a593Smuzhiyun and add "shared_" prefix. 42*4882a593Smuzhiyun 43*4882a593SmuzhiyunExample: 44*4882a593Smuzhiyun 45*4882a593SmuzhiyunDT entry: 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun vdpu: vdpu@ff650400 { 48*4882a593Smuzhiyun compatible = "rockchip,vpu-decoder-v2"; 49*4882a593Smuzhiyun reg = <0x0 0xff650400 0x0 0x400>; 50*4882a593Smuzhiyun interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 51*4882a593Smuzhiyun interrupt-names = "irq_dec"; 52*4882a593Smuzhiyun clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 53*4882a593Smuzhiyun clock-names = "aclk_vcodec", "hclk_vcodec"; 54*4882a593Smuzhiyun resets = <&cru SRST_H_VCODEC>, <&cru SRST_A_VCODEC>; 55*4882a593Smuzhiyun reset-names = "shared_video_h", "shared_video_a"; 56*4882a593Smuzhiyun iommus = <&vpu_mmu>; 57*4882a593Smuzhiyun power-domains = <&power RK3399_PD_VCODEC>; 58*4882a593Smuzhiyun rockchip,srv = <&mpp_srv>; 59*4882a593Smuzhiyun rockchip,taskqueue-node = <0>; 60*4882a593Smuzhiyun rockchip,resetgroup-node = <0>; 61*4882a593Smuzhiyun status = "disabled"; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun vepu: vepu@ff650000 { 65*4882a593Smuzhiyun compatible = "rockchip,vpu-encoder-v2"; 66*4882a593Smuzhiyun reg = <0x0 0xff650000 0x0 0x400>; 67*4882a593Smuzhiyun interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>; 68*4882a593Smuzhiyun interrupt-names = "irq_enc"; 69*4882a593Smuzhiyun clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 70*4882a593Smuzhiyun clock-names = "aclk_vcodec", "hclk_vcodec"; 71*4882a593Smuzhiyun resets = <&cru SRST_H_VCODEC>, <&cru SRST_A_VCODEC>; 72*4882a593Smuzhiyun reset-names = "shared_video_h", "shared_video_a"; 73*4882a593Smuzhiyun iommus = <&vpu_mmu>; 74*4882a593Smuzhiyun rockchip,srv = <&mpp_srv>; 75*4882a593Smuzhiyun rockchip,taskqueue-node = <0>; 76*4882a593Smuzhiyun rockchip,resetgroup-node = <0>; 77*4882a593Smuzhiyun power-domains = <&power RK3399_PD_VCODEC>; 78*4882a593Smuzhiyun status = "disabled"; 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun vpu_mmu: iommu@ff650800 { 82*4882a593Smuzhiyun compatible = "rockchip,iommu"; 83*4882a593Smuzhiyun reg = <0x0 0xff650800 0x0 0x40>; 84*4882a593Smuzhiyun interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>; 85*4882a593Smuzhiyun interrupt-names = "vpu_mmu"; 86*4882a593Smuzhiyun clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 87*4882a593Smuzhiyun clock-names = "aclk", "iface"; 88*4882a593Smuzhiyun power-domains = <&power RK3399_PD_VCODEC>; 89*4882a593Smuzhiyun #iommu-cells = <0>; 90*4882a593Smuzhiyun status = "disabled"; 91*4882a593Smuzhiyun }; 92