1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/usb/ti,hd3ss3220.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: TI HD3SS3220 TypeC DRP Port Controller 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Biju Das <biju.das.jz@bp.renesas.com> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyundescription: |- 13*4882a593Smuzhiyun HD3SS3220 is a USB SuperSpeed (SS) 2:1 mux with DRP port controller. The device provides Channel 14*4882a593Smuzhiyun Configuration (CC) logic and 5V VCONN sourcing for ecosystems implementing USB Type-C. The 15*4882a593Smuzhiyun HD3SS3220 can be configured as a Downstream Facing Port (DFP), Upstream Facing Port (UFP) or a 16*4882a593Smuzhiyun Dual Role Port (DRP) making it ideal for any application. 17*4882a593Smuzhiyun 18*4882a593Smuzhiyunproperties: 19*4882a593Smuzhiyun compatible: 20*4882a593Smuzhiyun const: ti,hd3ss3220 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun reg: 23*4882a593Smuzhiyun maxItems: 1 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun interrupts: 26*4882a593Smuzhiyun maxItems: 1 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun ports: 29*4882a593Smuzhiyun description: OF graph bindings (specified in bindings/graph.txt) that model 30*4882a593Smuzhiyun SS data bus to the SS capable connector. 31*4882a593Smuzhiyun type: object 32*4882a593Smuzhiyun properties: 33*4882a593Smuzhiyun port@0: 34*4882a593Smuzhiyun type: object 35*4882a593Smuzhiyun description: Super Speed (SS) MUX inputs connected to SS capable connector. 36*4882a593Smuzhiyun $ref: /connector/usb-connector.yaml#/properties/ports/properties/port@1 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun port@1: 39*4882a593Smuzhiyun type: object 40*4882a593Smuzhiyun description: Output of 2:1 MUX connected to Super Speed (SS) data bus. 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun required: 43*4882a593Smuzhiyun - port@0 44*4882a593Smuzhiyun - port@1 45*4882a593Smuzhiyun 46*4882a593Smuzhiyunrequired: 47*4882a593Smuzhiyun - compatible 48*4882a593Smuzhiyun - reg 49*4882a593Smuzhiyun - interrupts 50*4882a593Smuzhiyun 51*4882a593SmuzhiyunadditionalProperties: false 52*4882a593Smuzhiyun 53*4882a593Smuzhiyunexamples: 54*4882a593Smuzhiyun - | 55*4882a593Smuzhiyun i2c0 { 56*4882a593Smuzhiyun #address-cells = <1>; 57*4882a593Smuzhiyun #size-cells = <0>; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun hd3ss3220@47 { 60*4882a593Smuzhiyun compatible = "ti,hd3ss3220"; 61*4882a593Smuzhiyun reg = <0x47>; 62*4882a593Smuzhiyun interrupt-parent = <&gpio6>; 63*4882a593Smuzhiyun interrupts = <3>; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun ports { 66*4882a593Smuzhiyun #address-cells = <1>; 67*4882a593Smuzhiyun #size-cells = <0>; 68*4882a593Smuzhiyun port@0 { 69*4882a593Smuzhiyun reg = <0>; 70*4882a593Smuzhiyun hd3ss3220_in_ep: endpoint { 71*4882a593Smuzhiyun remote-endpoint = <&ss_ep>; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun port@1 { 75*4882a593Smuzhiyun reg = <1>; 76*4882a593Smuzhiyun hd3ss3220_out_ep: endpoint { 77*4882a593Smuzhiyun remote-endpoint = <&usb3_role_switch>; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun }; 83