1*4882a593SmuzhiyunRockchip SuperSpeed DWC3 USB SoC controller with INNO USB3 PHY inside 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible : should be one of the listed compatibles: 5*4882a593Smuzhiyun * "rockchip,rk3328-dwc3" 6*4882a593Smuzhiyun * "rockchip,rk322xh-dwc3" 7*4882a593Smuzhiyun- clocks : a list of phandle + clock-specifier pairs for the 8*4882a593Smuzhiyun clocks listed in clock-names. 9*4882a593Smuzhiyun- clock-names : Should contain the following: 10*4882a593Smuzhiyun * "ref_clk" for controller reference clk, have to be 24 MHz 11*4882a593Smuzhiyun * "suspend_clk" for controller suspend clk, have to be 24 MHz or 32 KHz 12*4882a593Smuzhiyun * "bus_clk" for master/Core clock, have to be >= 62.5 MHz for SS 13*4882a593Smuzhiyun operation and >= 30MHz for HS operation. 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunRequired child node: 16*4882a593SmuzhiyunA child node must exist to represent the core DWC3 IP block. The name of 17*4882a593Smuzhiyunthe node is not important. The content of the node is defined in dwc3.txt. 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunPhy documentation is provided in the following places: 20*4882a593SmuzhiyunDocumentation/devicetree/bindings/phy/phy-rockchip-inno-usb3.txt 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunExample device nodes: 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun u3phy: usb3-phy@ff470000 { 25*4882a593Smuzhiyun compatible = "rockchip,rk3328-u3phy"; 26*4882a593Smuzhiyun reg = <0x0 0xff470000 0x0 0x0>; 27*4882a593Smuzhiyun ... 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun u3phy_utmi: utmi@ff470000 { 30*4882a593Smuzhiyun reg = <0x0 0xff470000 0x0 0x8000>; 31*4882a593Smuzhiyun #phy-cells = <0>; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun u3phy_pipe: pipe@ff478000 { 35*4882a593Smuzhiyun reg = <0x0 0xff478000 0x0 0x8000>; 36*4882a593Smuzhiyun #phy-cells = <0>; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun usbdrd3: usb@ff600000 { 41*4882a593Smuzhiyun compatible = "rockchip,rk3328-dwc3"; 42*4882a593Smuzhiyun clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>, 43*4882a593Smuzhiyun <&cru ACLK_USB3OTG>; 44*4882a593Smuzhiyun clock-names = "ref_clk", "suspend_clk", 45*4882a593Smuzhiyun "bus_clk"; 46*4882a593Smuzhiyun #address-cells = <2>; 47*4882a593Smuzhiyun #size-cells = <2>; 48*4882a593Smuzhiyun ranges; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun usbdrd_dwc3: dwc3@ff600000 { 51*4882a593Smuzhiyun compatible = "snps,dwc3"; 52*4882a593Smuzhiyun reg = <0x0 0xff600000 0x0 0x100000>; 53*4882a593Smuzhiyun interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 54*4882a593Smuzhiyun dr_mode = "host"; 55*4882a593Smuzhiyun phys = <&u3phy_utmi>, <&u3phy_pipe>; 56*4882a593Smuzhiyun phy-names = "usb2-phy", "usb3-phy"; 57*4882a593Smuzhiyun phy_type = "utmi_wide"; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun }; 60