1*4882a593SmuzhiyunThe device node for Mediatek USB3.0 DRD controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun - compatible : should be "mediatek,<soc-model>-mtu3", "mediatek,mtu3", 5*4882a593Smuzhiyun soc-model is the name of SoC, such as mt8173, mt2712 etc, 6*4882a593Smuzhiyun when using "mediatek,mtu3" compatible string, you need SoC specific 7*4882a593Smuzhiyun ones in addition, one of: 8*4882a593Smuzhiyun - "mediatek,mt8173-mtu3" 9*4882a593Smuzhiyun - reg : specifies physical base address and size of the registers 10*4882a593Smuzhiyun - reg-names: should be "mac" for device IP and "ippc" for IP port control 11*4882a593Smuzhiyun - interrupts : interrupt used by the device IP 12*4882a593Smuzhiyun - power-domains : a phandle to USB power domain node to control USB's 13*4882a593Smuzhiyun mtcmos 14*4882a593Smuzhiyun - vusb33-supply : regulator of USB avdd3.3v 15*4882a593Smuzhiyun - clocks : a list of phandle + clock-specifier pairs, one for each 16*4882a593Smuzhiyun entry in clock-names 17*4882a593Smuzhiyun - clock-names : must contain "sys_ck" for clock of controller, 18*4882a593Smuzhiyun the following clocks are optional: 19*4882a593Smuzhiyun "ref_ck", "mcu_ck" and "dma_ck"; 20*4882a593Smuzhiyun - phys : see usb-hcd.yaml in the current directory 21*4882a593Smuzhiyun - dr_mode : should be one of "host", "peripheral" or "otg", 22*4882a593Smuzhiyun refer to usb/generic.txt 23*4882a593Smuzhiyun 24*4882a593SmuzhiyunOptional properties: 25*4882a593Smuzhiyun - #address-cells, #size-cells : should be '2' if the device has sub-nodes 26*4882a593Smuzhiyun with 'reg' property 27*4882a593Smuzhiyun - ranges : allows valid 1:1 translation between child's address space and 28*4882a593Smuzhiyun parent's address space 29*4882a593Smuzhiyun - extcon : external connector for vbus and idpin changes detection, needed 30*4882a593Smuzhiyun when supports dual-role mode. 31*4882a593Smuzhiyun it's considered valid for compatibility reasons, not allowed for 32*4882a593Smuzhiyun new bindings, and use "usb-role-switch" property instead. 33*4882a593Smuzhiyun - vbus-supply : reference to the VBUS regulator, needed when supports 34*4882a593Smuzhiyun dual-role mode. 35*4882a593Smuzhiyun it's considered valid for compatibility reasons, not allowed for 36*4882a593Smuzhiyun new bindings, and put into a usb-connector node. 37*4882a593Smuzhiyun see connector/usb-connector.yaml. 38*4882a593Smuzhiyun - pinctrl-names : a pinctrl state named "default" is optional, and need be 39*4882a593Smuzhiyun defined if auto drd switch is enabled, that means the property dr_mode 40*4882a593Smuzhiyun is set as "otg", and meanwhile the property "mediatek,enable-manual-drd" 41*4882a593Smuzhiyun is not set. 42*4882a593Smuzhiyun - pinctrl-0 : pin control group 43*4882a593Smuzhiyun See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun - maximum-speed : valid arguments are "super-speed", "high-speed" and 46*4882a593Smuzhiyun "full-speed"; refer to usb/generic.txt 47*4882a593Smuzhiyun - usb-role-switch : use USB Role Switch to support dual-role switch, but 48*4882a593Smuzhiyun not extcon; see usb/generic.txt. 49*4882a593Smuzhiyun - enable-manual-drd : supports manual dual-role switch via debugfs; usually 50*4882a593Smuzhiyun used when receptacle is TYPE-A and also wants to support dual-role 51*4882a593Smuzhiyun mode. 52*4882a593Smuzhiyun - wakeup-source: enable USB remote wakeup of host mode. 53*4882a593Smuzhiyun - mediatek,syscon-wakeup : phandle to syscon used to access the register 54*4882a593Smuzhiyun of the USB wakeup glue layer between SSUSB and SPM; it depends on 55*4882a593Smuzhiyun "wakeup-source", and has two arguments: 56*4882a593Smuzhiyun - the first one : register base address of the glue layer in syscon; 57*4882a593Smuzhiyun - the second one : hardware version of the glue layer 58*4882a593Smuzhiyun - 1 : used by mt8173 etc 59*4882a593Smuzhiyun - 2 : used by mt2712 etc 60*4882a593Smuzhiyun - mediatek,u3p-dis-msk : mask to disable u3ports, bit0 for u3port0, 61*4882a593Smuzhiyun bit1 for u3port1, ... etc; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyunadditionally the properties from usb-hcd.yaml (in the current directory) are 64*4882a593Smuzhiyunsupported. 65*4882a593Smuzhiyun 66*4882a593SmuzhiyunSub-nodes: 67*4882a593SmuzhiyunThe xhci should be added as subnode to mtu3 as shown in the following example 68*4882a593Smuzhiyunif host mode is enabled. The DT binding details of xhci can be found in: 69*4882a593SmuzhiyunDocumentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt 70*4882a593Smuzhiyun 71*4882a593SmuzhiyunThe port would be added as subnode if use "usb-role-switch" property. 72*4882a593Smuzhiyun see graph.txt 73*4882a593Smuzhiyun 74*4882a593SmuzhiyunExample: 75*4882a593Smuzhiyunssusb: usb@11271000 { 76*4882a593Smuzhiyun compatible = "mediatek,mt8173-mtu3"; 77*4882a593Smuzhiyun reg = <0 0x11271000 0 0x3000>, 78*4882a593Smuzhiyun <0 0x11280700 0 0x0100>; 79*4882a593Smuzhiyun reg-names = "mac", "ippc"; 80*4882a593Smuzhiyun interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>; 81*4882a593Smuzhiyun phys = <&phy_port0 PHY_TYPE_USB3>, 82*4882a593Smuzhiyun <&phy_port1 PHY_TYPE_USB2>; 83*4882a593Smuzhiyun power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; 84*4882a593Smuzhiyun clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>, 85*4882a593Smuzhiyun <&pericfg CLK_PERI_USB0>, 86*4882a593Smuzhiyun <&pericfg CLK_PERI_USB1>; 87*4882a593Smuzhiyun clock-names = "sys_ck", "ref_ck"; 88*4882a593Smuzhiyun vusb33-supply = <&mt6397_vusb_reg>; 89*4882a593Smuzhiyun vbus-supply = <&usb_p0_vbus>; 90*4882a593Smuzhiyun extcon = <&extcon_usb>; 91*4882a593Smuzhiyun dr_mode = "otg"; 92*4882a593Smuzhiyun wakeup-source; 93*4882a593Smuzhiyun mediatek,syscon-wakeup = <&pericfg 0x400 1>; 94*4882a593Smuzhiyun #address-cells = <2>; 95*4882a593Smuzhiyun #size-cells = <2>; 96*4882a593Smuzhiyun ranges; 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun usb_host: xhci@11270000 { 99*4882a593Smuzhiyun compatible = "mediatek,mt8173-xhci"; 100*4882a593Smuzhiyun reg = <0 0x11270000 0 0x1000>; 101*4882a593Smuzhiyun reg-names = "mac"; 102*4882a593Smuzhiyun interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; 103*4882a593Smuzhiyun power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; 104*4882a593Smuzhiyun clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; 105*4882a593Smuzhiyun clock-names = "sys_ck", "ref_ck"; 106*4882a593Smuzhiyun vusb33-supply = <&mt6397_vusb_reg>; 107*4882a593Smuzhiyun }; 108*4882a593Smuzhiyun}; 109