xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593SmuzhiyunMT8173 xHCI
2*4882a593Smuzhiyun
3*4882a593SmuzhiyunThe device node for Mediatek SOC USB3.0 host controller
4*4882a593Smuzhiyun
5*4882a593SmuzhiyunThere are two scenarios: the first one only supports xHCI driver;
6*4882a593Smuzhiyunthe second one supports dual-role mode, and the host is based on xHCI
7*4882a593Smuzhiyundriver. Take account of backward compatibility, we divide bindings
8*4882a593Smuzhiyuninto two parts.
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun1st: only supports xHCI driver
11*4882a593Smuzhiyun------------------------------------------------------------------------
12*4882a593Smuzhiyun
13*4882a593SmuzhiyunRequired properties:
14*4882a593Smuzhiyun - compatible : should be "mediatek,<soc-model>-xhci", "mediatek,mtk-xhci",
15*4882a593Smuzhiyun	soc-model is the name of SoC, such as mt8173, mt2712 etc, when using
16*4882a593Smuzhiyun	"mediatek,mtk-xhci" compatible string, you need SoC specific ones in
17*4882a593Smuzhiyun	addition, one of:
18*4882a593Smuzhiyun	- "mediatek,mt8173-xhci"
19*4882a593Smuzhiyun - reg : specifies physical base address and size of the registers
20*4882a593Smuzhiyun - reg-names: should be "mac" for xHCI MAC and "ippc" for IP port control
21*4882a593Smuzhiyun - interrupts : interrupt used by the controller
22*4882a593Smuzhiyun - power-domains : a phandle to USB power domain node to control USB's
23*4882a593Smuzhiyun	mtcmos
24*4882a593Smuzhiyun - vusb33-supply : regulator of USB avdd3.3v
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun - clocks : a list of phandle + clock-specifier pairs, one for each
27*4882a593Smuzhiyun	entry in clock-names
28*4882a593Smuzhiyun - clock-names : must contain
29*4882a593Smuzhiyun	"sys_ck": controller clock used by normal mode,
30*4882a593Smuzhiyun	the following ones are optional:
31*4882a593Smuzhiyun	"ref_ck": reference clock used by low power mode etc,
32*4882a593Smuzhiyun	"mcu_ck": mcu_bus clock for register access,
33*4882a593Smuzhiyun	"dma_ck": dma_bus clock for data transfer by DMA,
34*4882a593Smuzhiyun	"xhci_ck": controller clock
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun - phys : see usb-hcd.yaml in the current directory
37*4882a593Smuzhiyun
38*4882a593SmuzhiyunOptional properties:
39*4882a593Smuzhiyun - wakeup-source : enable USB remote wakeup;
40*4882a593Smuzhiyun - mediatek,syscon-wakeup : phandle to syscon used to access the register
41*4882a593Smuzhiyun	of the USB wakeup glue layer between xHCI and SPM; it depends on
42*4882a593Smuzhiyun	"wakeup-source", and has two arguments:
43*4882a593Smuzhiyun	- the first one : register base address of the glue layer in syscon;
44*4882a593Smuzhiyun	- the second one : hardware version of the glue layer
45*4882a593Smuzhiyun		- 1 : used by mt8173 etc
46*4882a593Smuzhiyun		- 2 : used by mt2712 etc
47*4882a593Smuzhiyun - mediatek,u3p-dis-msk : mask to disable u3ports, bit0 for u3port0,
48*4882a593Smuzhiyun	bit1 for u3port1, ... etc;
49*4882a593Smuzhiyun - vbus-supply : reference to the VBUS regulator;
50*4882a593Smuzhiyun - usb3-lpm-capable : supports USB3.0 LPM
51*4882a593Smuzhiyun - pinctrl-names : a pinctrl state named "default" must be defined
52*4882a593Smuzhiyun - pinctrl-0 : pin control group
53*4882a593Smuzhiyun	See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
54*4882a593Smuzhiyun - imod-interval-ns: default interrupt moderation interval is 5000ns
55*4882a593Smuzhiyun
56*4882a593Smuzhiyunadditionally the properties from usb-hcd.yaml (in the current directory) are
57*4882a593Smuzhiyunsupported.
58*4882a593Smuzhiyun
59*4882a593SmuzhiyunExample:
60*4882a593Smuzhiyunusb30: usb@11270000 {
61*4882a593Smuzhiyun	compatible = "mediatek,mt8173-xhci";
62*4882a593Smuzhiyun	reg = <0 0x11270000 0 0x1000>,
63*4882a593Smuzhiyun	      <0 0x11280700 0 0x0100>;
64*4882a593Smuzhiyun	reg-names = "mac", "ippc";
65*4882a593Smuzhiyun	interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
66*4882a593Smuzhiyun	power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
67*4882a593Smuzhiyun	clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>,
68*4882a593Smuzhiyun		 <&pericfg CLK_PERI_USB0>,
69*4882a593Smuzhiyun		 <&pericfg CLK_PERI_USB1>;
70*4882a593Smuzhiyun	clock-names = "sys_ck", "ref_ck";
71*4882a593Smuzhiyun	phys = <&phy_port0 PHY_TYPE_USB3>,
72*4882a593Smuzhiyun	       <&phy_port1 PHY_TYPE_USB2>;
73*4882a593Smuzhiyun	vusb33-supply = <&mt6397_vusb_reg>;
74*4882a593Smuzhiyun	vbus-supply = <&usb_p1_vbus>;
75*4882a593Smuzhiyun	usb3-lpm-capable;
76*4882a593Smuzhiyun	mediatek,syscon-wakeup = <&pericfg 0x400 1>;
77*4882a593Smuzhiyun	wakeup-source;
78*4882a593Smuzhiyun	imod-interval-ns = <10000>;
79*4882a593Smuzhiyun};
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun2nd: dual-role mode with xHCI driver
82*4882a593Smuzhiyun------------------------------------------------------------------------
83*4882a593Smuzhiyun
84*4882a593SmuzhiyunIn the case, xhci is added as subnode to mtu3. An example and the DT binding
85*4882a593Smuzhiyundetails of mtu3 can be found in:
86*4882a593SmuzhiyunDocumentation/devicetree/bindings/usb/mediatek,mtu3.txt
87*4882a593Smuzhiyun
88*4882a593SmuzhiyunRequired properties:
89*4882a593Smuzhiyun - compatible : should be "mediatek,<soc-model>-xhci", "mediatek,mtk-xhci",
90*4882a593Smuzhiyun	soc-model is the name of SoC, such as mt8173, mt2712 etc, when using
91*4882a593Smuzhiyun	"mediatek,mtk-xhci" compatible string, you need SoC specific ones in
92*4882a593Smuzhiyun	addition, one of:
93*4882a593Smuzhiyun	- "mediatek,mt8173-xhci"
94*4882a593Smuzhiyun - reg : specifies physical base address and size of the registers
95*4882a593Smuzhiyun - reg-names: should be "mac" for xHCI MAC
96*4882a593Smuzhiyun - interrupts : interrupt used by the host controller
97*4882a593Smuzhiyun - power-domains : a phandle to USB power domain node to control USB's
98*4882a593Smuzhiyun	mtcmos
99*4882a593Smuzhiyun - vusb33-supply : regulator of USB avdd3.3v
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun - clocks : a list of phandle + clock-specifier pairs, one for each
102*4882a593Smuzhiyun	entry in clock-names
103*4882a593Smuzhiyun - clock-names : must contain "sys_ck", and the following ones are optional:
104*4882a593Smuzhiyun	"ref_ck", "mcu_ck" and "dma_ck", "xhci_ck"
105*4882a593Smuzhiyun
106*4882a593SmuzhiyunOptional properties:
107*4882a593Smuzhiyun - vbus-supply : reference to the VBUS regulator;
108*4882a593Smuzhiyun - usb3-lpm-capable : supports USB3.0 LPM
109*4882a593Smuzhiyun
110*4882a593SmuzhiyunExample:
111*4882a593Smuzhiyunusb30: usb@11270000 {
112*4882a593Smuzhiyun	compatible = "mediatek,mt8173-xhci";
113*4882a593Smuzhiyun	reg = <0 0x11270000 0 0x1000>;
114*4882a593Smuzhiyun	reg-names = "mac";
115*4882a593Smuzhiyun	interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
116*4882a593Smuzhiyun	power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
117*4882a593Smuzhiyun	clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
118*4882a593Smuzhiyun	clock-names = "sys_ck", "ref_ck";
119*4882a593Smuzhiyun	vusb33-supply = <&mt6397_vusb_reg>;
120*4882a593Smuzhiyun	usb3-lpm-capable;
121*4882a593Smuzhiyun};
122