1*4882a593Smuzhiyun* NXP LPC32xx SoC USB Device Controller (UDC) 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: Must be "nxp,lpc3220-udc" 5*4882a593Smuzhiyun- reg: Physical base address of the controller and length of memory mapped 6*4882a593Smuzhiyun region. 7*4882a593Smuzhiyun- interrupts: The USB interrupts: 8*4882a593Smuzhiyun * USB Device Low Priority Interrupt 9*4882a593Smuzhiyun * USB Device High Priority Interrupt 10*4882a593Smuzhiyun * USB Device DMA Interrupt 11*4882a593Smuzhiyun * External USB Transceiver Interrupt (OTG ATX) 12*4882a593Smuzhiyun- transceiver: phandle of the associated ISP1301 device - this is necessary for 13*4882a593Smuzhiyun the UDC controller for connecting to the USB physical layer 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunExample: 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun isp1301: usb-transceiver@2c { 18*4882a593Smuzhiyun compatible = "nxp,isp1301"; 19*4882a593Smuzhiyun reg = <0x2c>; 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun usbd@31020000 { 23*4882a593Smuzhiyun compatible = "nxp,lpc3220-udc"; 24*4882a593Smuzhiyun reg = <0x31020000 0x300>; 25*4882a593Smuzhiyun interrupt-parent = <&mic>; 26*4882a593Smuzhiyun interrupts = <0x3d 0>, <0x3e 0>, <0x3c 0>, <0x3a 0>; 27*4882a593Smuzhiyun transceiver = <&isp1301>; 28*4882a593Smuzhiyun }; 29