1*4882a593SmuzhiyunFreescale SOC USB controllers 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe device node for a USB controller that is part of a Freescale 4*4882a593SmuzhiyunSOC is as described in the document "Open Firmware Recommended 5*4882a593SmuzhiyunPractice : Universal Serial Bus" with the following modifications 6*4882a593Smuzhiyunand additions : 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunRequired properties : 9*4882a593Smuzhiyun - compatible : Should be "fsl-usb2-mph" for multi port host USB 10*4882a593Smuzhiyun controllers, or "fsl-usb2-dr" for dual role USB controllers 11*4882a593Smuzhiyun or "fsl,mpc5121-usb2-dr" for dual role USB controllers of MPC5121. 12*4882a593Smuzhiyun Wherever applicable, the IP version of the USB controller should 13*4882a593Smuzhiyun also be mentioned (for eg. fsl-usb2-dr-v2.2 for bsc9132). 14*4882a593Smuzhiyun - phy_type : For multi port host USB controllers, should be one of 15*4882a593Smuzhiyun "ulpi", or "serial". For dual role USB controllers, should be 16*4882a593Smuzhiyun one of "ulpi", "utmi", "utmi_wide", or "serial". 17*4882a593Smuzhiyun - reg : Offset and length of the register set for the device 18*4882a593Smuzhiyun - port0 : boolean; if defined, indicates port0 is connected for 19*4882a593Smuzhiyun fsl-usb2-mph compatible controllers. Either this property or 20*4882a593Smuzhiyun "port1" (or both) must be defined for "fsl-usb2-mph" compatible 21*4882a593Smuzhiyun controllers. 22*4882a593Smuzhiyun - port1 : boolean; if defined, indicates port1 is connected for 23*4882a593Smuzhiyun fsl-usb2-mph compatible controllers. Either this property or 24*4882a593Smuzhiyun "port0" (or both) must be defined for "fsl-usb2-mph" compatible 25*4882a593Smuzhiyun controllers. 26*4882a593Smuzhiyun - dr_mode : indicates the working mode for "fsl-usb2-dr" compatible 27*4882a593Smuzhiyun controllers. Can be "host", "peripheral", or "otg". Default to 28*4882a593Smuzhiyun "host" if not defined for backward compatibility. 29*4882a593Smuzhiyun 30*4882a593SmuzhiyunRecommended properties : 31*4882a593Smuzhiyun - interrupts : <a b> where a is the interrupt number and b is a 32*4882a593Smuzhiyun field that represents an encoding of the sense and level 33*4882a593Smuzhiyun information for the interrupt. This should be encoded based on 34*4882a593Smuzhiyun the information in section 2) depending on the type of interrupt 35*4882a593Smuzhiyun controller you have. 36*4882a593Smuzhiyun 37*4882a593SmuzhiyunOptional properties : 38*4882a593Smuzhiyun - fsl,invert-drvvbus : boolean; for MPC5121 USB0 only. Indicates the 39*4882a593Smuzhiyun port power polarity of internal PHY signal DRVVBUS is inverted. 40*4882a593Smuzhiyun - fsl,invert-pwr-fault : boolean; for MPC5121 USB0 only. Indicates 41*4882a593Smuzhiyun the PWR_FAULT signal polarity is inverted. 42*4882a593Smuzhiyun 43*4882a593SmuzhiyunExample multi port host USB controller device node : 44*4882a593Smuzhiyun usb@22000 { 45*4882a593Smuzhiyun compatible = "fsl-usb2-mph"; 46*4882a593Smuzhiyun reg = <22000 1000>; 47*4882a593Smuzhiyun #address-cells = <1>; 48*4882a593Smuzhiyun #size-cells = <0>; 49*4882a593Smuzhiyun interrupt-parent = <700>; 50*4882a593Smuzhiyun interrupts = <27 1>; 51*4882a593Smuzhiyun phy_type = "ulpi"; 52*4882a593Smuzhiyun port0; 53*4882a593Smuzhiyun port1; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun 56*4882a593SmuzhiyunExample dual role USB controller device node : 57*4882a593Smuzhiyun usb@23000 { 58*4882a593Smuzhiyun compatible = "fsl-usb2-dr"; 59*4882a593Smuzhiyun reg = <23000 1000>; 60*4882a593Smuzhiyun #address-cells = <1>; 61*4882a593Smuzhiyun #size-cells = <0>; 62*4882a593Smuzhiyun interrupt-parent = <700>; 63*4882a593Smuzhiyun interrupts = <26 1>; 64*4882a593Smuzhiyun dr_mode = "otg"; 65*4882a593Smuzhiyun phy = "ulpi"; 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun 68*4882a593SmuzhiyunExample dual role USB controller device node for MPC5121ADS: 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun usb@4000 { 71*4882a593Smuzhiyun compatible = "fsl,mpc5121-usb2-dr"; 72*4882a593Smuzhiyun reg = <0x4000 0x1000>; 73*4882a593Smuzhiyun #address-cells = <1>; 74*4882a593Smuzhiyun #size-cells = <0>; 75*4882a593Smuzhiyun interrupt-parent = < &ipic >; 76*4882a593Smuzhiyun interrupts = <44 0x8>; 77*4882a593Smuzhiyun dr_mode = "otg"; 78*4882a593Smuzhiyun phy_type = "utmi_wide"; 79*4882a593Smuzhiyun fsl,invert-drvvbus; 80*4882a593Smuzhiyun fsl,invert-pwr-fault; 81*4882a593Smuzhiyun }; 82