1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun# Copyright (c) 2020 NXP 3*4882a593Smuzhiyun%YAML 1.2 4*4882a593Smuzhiyun--- 5*4882a593Smuzhiyun$id: http://devicetree.org/schemas/usb/fsl,imx8mp-dwc3.yaml# 6*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 7*4882a593Smuzhiyun 8*4882a593Smuzhiyuntitle: NXP iMX8MP Soc USB Controller 9*4882a593Smuzhiyun 10*4882a593Smuzhiyunmaintainers: 11*4882a593Smuzhiyun - Li Jun <jun.li@nxp.com> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyunproperties: 14*4882a593Smuzhiyun compatible: 15*4882a593Smuzhiyun const: fsl,imx8mp-dwc3 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun reg: 18*4882a593Smuzhiyun maxItems: 1 19*4882a593Smuzhiyun description: Address and length of the register set for the wrapper of 20*4882a593Smuzhiyun dwc3 core on the SOC. 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun "#address-cells": 23*4882a593Smuzhiyun enum: [ 1, 2 ] 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun "#size-cells": 26*4882a593Smuzhiyun enum: [ 1, 2 ] 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun dma-ranges: 29*4882a593Smuzhiyun description: 30*4882a593Smuzhiyun See section 2.3.9 of the DeviceTree Specification. 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun ranges: true 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun interrupts: 35*4882a593Smuzhiyun maxItems: 1 36*4882a593Smuzhiyun description: The interrupt that is asserted when a wakeup event is 37*4882a593Smuzhiyun received. 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun clocks: 40*4882a593Smuzhiyun description: 41*4882a593Smuzhiyun A list of phandle and clock-specifier pairs for the clocks 42*4882a593Smuzhiyun listed in clock-names. 43*4882a593Smuzhiyun items: 44*4882a593Smuzhiyun - description: system hsio root clock. 45*4882a593Smuzhiyun - description: suspend clock, used for usb wakeup logic. 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun clock-names: 48*4882a593Smuzhiyun items: 49*4882a593Smuzhiyun - const: hsio 50*4882a593Smuzhiyun - const: suspend 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun# Required child node: 53*4882a593Smuzhiyun 54*4882a593SmuzhiyunpatternProperties: 55*4882a593Smuzhiyun "^dwc3@[0-9a-f]+$": 56*4882a593Smuzhiyun type: object 57*4882a593Smuzhiyun description: 58*4882a593Smuzhiyun A child node must exist to represent the core DWC3 IP block 59*4882a593Smuzhiyun The content of the node is defined in dwc3.txt. 60*4882a593Smuzhiyun 61*4882a593Smuzhiyunrequired: 62*4882a593Smuzhiyun - compatible 63*4882a593Smuzhiyun - reg 64*4882a593Smuzhiyun - "#address-cells" 65*4882a593Smuzhiyun - "#size-cells" 66*4882a593Smuzhiyun - dma-ranges 67*4882a593Smuzhiyun - ranges 68*4882a593Smuzhiyun - clocks 69*4882a593Smuzhiyun - clock-names 70*4882a593Smuzhiyun - interrupts 71*4882a593Smuzhiyun 72*4882a593SmuzhiyunadditionalProperties: false 73*4882a593Smuzhiyun 74*4882a593Smuzhiyunexamples: 75*4882a593Smuzhiyun - | 76*4882a593Smuzhiyun #include <dt-bindings/clock/imx8mp-clock.h> 77*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/arm-gic.h> 78*4882a593Smuzhiyun usb3_0: usb@32f10100 { 79*4882a593Smuzhiyun compatible = "fsl,imx8mp-dwc3"; 80*4882a593Smuzhiyun reg = <0x32f10100 0x8>; 81*4882a593Smuzhiyun clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 82*4882a593Smuzhiyun <&clk IMX8MP_CLK_USB_ROOT>; 83*4882a593Smuzhiyun clock-names = "hsio", "suspend"; 84*4882a593Smuzhiyun interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 85*4882a593Smuzhiyun #address-cells = <1>; 86*4882a593Smuzhiyun #size-cells = <1>; 87*4882a593Smuzhiyun dma-ranges = <0x40000000 0x40000000 0xc0000000>; 88*4882a593Smuzhiyun ranges; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun dwc3@38100000 { 91*4882a593Smuzhiyun compatible = "snps,dwc3"; 92*4882a593Smuzhiyun reg = <0x38100000 0x10000>; 93*4882a593Smuzhiyun clocks = <&clk IMX8MP_CLK_HSIO_AXI>, 94*4882a593Smuzhiyun <&clk IMX8MP_CLK_USB_CORE_REF>, 95*4882a593Smuzhiyun <&clk IMX8MP_CLK_USB_ROOT>; 96*4882a593Smuzhiyun clock-names = "bus_early", "ref", "suspend"; 97*4882a593Smuzhiyun assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>; 98*4882a593Smuzhiyun assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; 99*4882a593Smuzhiyun assigned-clock-rates = <500000000>; 100*4882a593Smuzhiyun interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 101*4882a593Smuzhiyun phys = <&usb3_phy0>, <&usb3_phy0>; 102*4882a593Smuzhiyun phy-names = "usb2-phy", "usb3-phy"; 103*4882a593Smuzhiyun snps,dis-u2-freeclk-exists-quirk; 104*4882a593Smuzhiyun }; 105*4882a593Smuzhiyun }; 106