1*4882a593SmuzhiyunXilinx SuperSpeed DWC3 USB SoC controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: Should contain "xlnx,zynqmp-dwc3" 5*4882a593Smuzhiyun- clocks: A list of phandles for the clocks listed in clock-names 6*4882a593Smuzhiyun- clock-names: Should contain the following: 7*4882a593Smuzhiyun "bus_clk" Master/Core clock, have to be >= 125 MHz for SS 8*4882a593Smuzhiyun operation and >= 60MHz for HS operation 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun "ref_clk" Clock source to core during PHY power down 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunRequired child node: 13*4882a593SmuzhiyunA child node must exist to represent the core DWC3 IP block. The name of 14*4882a593Smuzhiyunthe node is not important. The content of the node is defined in dwc3.txt. 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunExample device node: 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun usb@0 { 19*4882a593Smuzhiyun #address-cells = <0x2>; 20*4882a593Smuzhiyun #size-cells = <0x1>; 21*4882a593Smuzhiyun compatible = "xlnx,zynqmp-dwc3"; 22*4882a593Smuzhiyun clock-names = "bus_clk" "ref_clk"; 23*4882a593Smuzhiyun clocks = <&clk125>, <&clk125>; 24*4882a593Smuzhiyun ranges; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun dwc3@fe200000 { 27*4882a593Smuzhiyun compatible = "snps,dwc3"; 28*4882a593Smuzhiyun reg = <0x0 0xfe200000 0x40000>; 29*4882a593Smuzhiyun interrupts = <0x0 0x41 0x4>; 30*4882a593Smuzhiyun dr_mode = "host"; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun }; 33