1*4882a593SmuzhiyunCavium SuperSpeed DWC3 USB SoC controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: Should contain "cavium,octeon-7130-usb-uctl" 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired child node: 7*4882a593SmuzhiyunA child node must exist to represent the core DWC3 IP block. The name of 8*4882a593Smuzhiyunthe node is not important. The content of the node is defined in dwc3.txt. 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunExample device node: 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun uctl@1180069000000 { 13*4882a593Smuzhiyun compatible = "cavium,octeon-7130-usb-uctl"; 14*4882a593Smuzhiyun reg = <0x00011800 0x69000000 0x00000000 0x00000100>; 15*4882a593Smuzhiyun ranges; 16*4882a593Smuzhiyun #address-cells = <0x00000002>; 17*4882a593Smuzhiyun #size-cells = <0x00000002>; 18*4882a593Smuzhiyun refclk-frequency = <0x05f5e100>; 19*4882a593Smuzhiyun refclk-type-ss = "dlmc_ref_clk0"; 20*4882a593Smuzhiyun refclk-type-hs = "dlmc_ref_clk0"; 21*4882a593Smuzhiyun power = <0x00000002 0x00000002 0x00000001>; 22*4882a593Smuzhiyun xhci@1690000000000 { 23*4882a593Smuzhiyun compatible = "cavium,octeon-7130-xhci", "synopsys,dwc3"; 24*4882a593Smuzhiyun reg = <0x00016900 0x00000000 0x00000010 0x00000000>; 25*4882a593Smuzhiyun interrupt-parent = <0x00000010>; 26*4882a593Smuzhiyun interrupts = <0x00000009 0x00000004>; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun }; 29