1*4882a593Smuzhiyun* Qualcomm Technologies Inc Universal Flash Storage (UFS) PHY 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunUFSPHY nodes are defined to describe on-chip UFS PHY hardware macro. 4*4882a593SmuzhiyunEach UFS PHY node should have its own node. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunTo bind UFS PHY with UFS host controller, the controller node should 7*4882a593Smuzhiyuncontain a phandle reference to UFS PHY node. 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunRequired properties: 10*4882a593Smuzhiyun- compatible : compatible list, contains one of the following - 11*4882a593Smuzhiyun "qcom,ufs-phy-qmp-20nm" for 20nm ufs phy, 12*4882a593Smuzhiyun "qcom,ufs-phy-qmp-14nm" for legacy 14nm ufs phy, 13*4882a593Smuzhiyun "qcom,msm8996-ufs-phy-qmp-14nm" for 14nm ufs phy 14*4882a593Smuzhiyun present on MSM8996 chipset. 15*4882a593Smuzhiyun- reg : should contain PHY register address space (mandatory), 16*4882a593Smuzhiyun- reg-names : indicates various resources passed to driver (via reg proptery) by name. 17*4882a593Smuzhiyun Required "reg-names" is "phy_mem". 18*4882a593Smuzhiyun- #phy-cells : This property shall be set to 0 19*4882a593Smuzhiyun- vdda-phy-supply : phandle to main PHY supply for analog domain 20*4882a593Smuzhiyun- vdda-pll-supply : phandle to PHY PLL and Power-Gen block power supply 21*4882a593Smuzhiyun- clocks : List of phandle and clock specifier pairs 22*4882a593Smuzhiyun- clock-names : List of clock input name strings sorted in the same 23*4882a593Smuzhiyun order as the clocks property. "ref_clk_src", "ref_clk", 24*4882a593Smuzhiyun "tx_iface_clk" & "rx_iface_clk" are mandatory but 25*4882a593Smuzhiyun "ref_clk_parent" is optional 26*4882a593Smuzhiyun 27*4882a593SmuzhiyunOptional properties: 28*4882a593Smuzhiyun- vdda-phy-max-microamp : specifies max. load that can be drawn from phy supply 29*4882a593Smuzhiyun- vdda-pll-max-microamp : specifies max. load that can be drawn from pll supply 30*4882a593Smuzhiyun- vddp-ref-clk-supply : phandle to UFS device ref_clk pad power supply 31*4882a593Smuzhiyun- vddp-ref-clk-max-microamp : specifies max. load that can be drawn from this supply 32*4882a593Smuzhiyun- resets : specifies the PHY reset in the UFS controller 33*4882a593Smuzhiyun 34*4882a593SmuzhiyunExample: 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun ufsphy1: ufsphy@fc597000 { 37*4882a593Smuzhiyun compatible = "qcom,ufs-phy-qmp-20nm"; 38*4882a593Smuzhiyun reg = <0xfc597000 0x800>; 39*4882a593Smuzhiyun reg-names = "phy_mem"; 40*4882a593Smuzhiyun #phy-cells = <0>; 41*4882a593Smuzhiyun vdda-phy-supply = <&pma8084_l4>; 42*4882a593Smuzhiyun vdda-pll-supply = <&pma8084_l12>; 43*4882a593Smuzhiyun vdda-phy-max-microamp = <50000>; 44*4882a593Smuzhiyun vdda-pll-max-microamp = <1000>; 45*4882a593Smuzhiyun clock-names = "ref_clk_src", 46*4882a593Smuzhiyun "ref_clk_parent", 47*4882a593Smuzhiyun "ref_clk", 48*4882a593Smuzhiyun "tx_iface_clk", 49*4882a593Smuzhiyun "rx_iface_clk"; 50*4882a593Smuzhiyun clocks = <&clock_rpm clk_ln_bb_clk>, 51*4882a593Smuzhiyun <&clock_gcc clk_pcie_1_phy_ldo >, 52*4882a593Smuzhiyun <&clock_gcc clk_ufs_phy_ldo>, 53*4882a593Smuzhiyun <&clock_gcc clk_gcc_ufs_tx_cfg_clk>, 54*4882a593Smuzhiyun <&clock_gcc clk_gcc_ufs_rx_cfg_clk>; 55*4882a593Smuzhiyun resets = <&ufshc 0>; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun ufshc: ufshc@fc598000 { 59*4882a593Smuzhiyun #reset-cells = <1>; 60*4882a593Smuzhiyun ... 61*4882a593Smuzhiyun phys = <&ufsphy1>; 62*4882a593Smuzhiyun phy-names = "ufsphy"; 63*4882a593Smuzhiyun }; 64