1*4882a593Smuzhiyun* Mediatek Universal Flash Storage (UFS) Host Controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunUFS nodes are defined to describe on-chip UFS hardware macro. 4*4882a593SmuzhiyunEach UFS Host Controller should have its own node. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunTo bind UFS PHY with UFS host controller, the controller node should 7*4882a593Smuzhiyuncontain a phandle reference to UFS M-PHY node. 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunRequired properties for UFS nodes: 10*4882a593Smuzhiyun- compatible : Compatible list, contains the following controller: 11*4882a593Smuzhiyun "mediatek,mt8183-ufshci" for MediaTek UFS host controller 12*4882a593Smuzhiyun present on MT8183 chipsets. 13*4882a593Smuzhiyun "mediatek,mt8192-ufshci" for MediaTek UFS host controller 14*4882a593Smuzhiyun present on MT8192 chipsets. 15*4882a593Smuzhiyun- reg : Address and length of the UFS register set. 16*4882a593Smuzhiyun- phys : phandle to m-phy. 17*4882a593Smuzhiyun- clocks : List of phandle and clock specifier pairs. 18*4882a593Smuzhiyun- clock-names : List of clock input name strings sorted in the same 19*4882a593Smuzhiyun order as the clocks property. "ufs" is mandatory. 20*4882a593Smuzhiyun "ufs": ufshci core control clock. 21*4882a593Smuzhiyun- freq-table-hz : Array of <min max> operating frequencies stored in the same 22*4882a593Smuzhiyun order as the clocks property. If this property is not 23*4882a593Smuzhiyun defined or a value in the array is "0" then it is assumed 24*4882a593Smuzhiyun that the frequency is set by the parent clock or a 25*4882a593Smuzhiyun fixed rate clock source. 26*4882a593Smuzhiyun- vcc-supply : phandle to VCC supply regulator node. 27*4882a593Smuzhiyun 28*4882a593SmuzhiyunExample: 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun ufsphy: phy@11fa0000 { 31*4882a593Smuzhiyun ... 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun ufshci@11270000 { 35*4882a593Smuzhiyun compatible = "mediatek,mt8183-ufshci"; 36*4882a593Smuzhiyun reg = <0 0x11270000 0 0x2300>; 37*4882a593Smuzhiyun interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>; 38*4882a593Smuzhiyun phys = <&ufsphy>; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun clocks = <&infracfg_ao INFRACFG_AO_UFS_CG>; 41*4882a593Smuzhiyun clock-names = "ufs"; 42*4882a593Smuzhiyun freq-table-hz = <0 0>; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun vcc-supply = <&mt_pmic_vemc_ldo_reg>; 45*4882a593Smuzhiyun }; 46