1*4882a593Smuzhiyun* Universal Flash Storage (UFS) DesignWare Host Controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunDWC_UFS nodes are defined to describe on-chip UFS host controllers and MPHY. 4*4882a593SmuzhiyunEach UFS controller instance should have its own node. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired properties: 7*4882a593Smuzhiyun- compatible : compatible list must contain the PHY type & version: 8*4882a593Smuzhiyun "snps,g210-tc-6.00-20bit" 9*4882a593Smuzhiyun "snps,g210-tc-6.00-40bit" 10*4882a593Smuzhiyun complemented with the Controller IP version: 11*4882a593Smuzhiyun "snps,dwc-ufshcd-1.40a" 12*4882a593Smuzhiyun complemented with the JEDEC version: 13*4882a593Smuzhiyun "jedec,ufs-1.1" 14*4882a593Smuzhiyun "jedec,ufs-2.0" 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun- reg : <registers mapping> 17*4882a593Smuzhiyun- interrupts : <interrupt mapping for UFS host controller IRQ> 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunExample for a setup using a 1.40a DWC Controller with a 6.00 G210 40-bit TC: 20*4882a593Smuzhiyun dwc-ufs@d0000000 { 21*4882a593Smuzhiyun compatible = "snps,g210-tc-6.00-40bit", 22*4882a593Smuzhiyun "snps,dwc-ufshcd-1.40a", 23*4882a593Smuzhiyun "jedec,ufs-2.0"; 24*4882a593Smuzhiyun reg = < 0xd0000000 0x10000 >; 25*4882a593Smuzhiyun interrupts = < 24 >; 26*4882a593Smuzhiyun }; 27