1*4882a593Smuzhiyun* Cadence Universal Flash Storage (UFS) Controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunUFS nodes are defined to describe on-chip UFS host controllers. 4*4882a593SmuzhiyunEach UFS controller instance should have its own node. 5*4882a593SmuzhiyunPlease see the ufshcd-pltfrm.txt for a list of all available properties. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunRequired properties: 8*4882a593Smuzhiyun- compatible : Compatible list, contains one of the following controllers: 9*4882a593Smuzhiyun "cdns,ufshc" - Generic CDNS HCI, 10*4882a593Smuzhiyun "cdns,ufshc-m31-16nm" - CDNS UFS HC + M31 16nm PHY 11*4882a593Smuzhiyun complemented with the JEDEC version: 12*4882a593Smuzhiyun "jedec,ufs-2.0" 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun- reg : Address and length of the UFS register set. 15*4882a593Smuzhiyun- interrupts : One interrupt mapping. 16*4882a593Smuzhiyun- freq-table-hz : Clock frequency table. 17*4882a593Smuzhiyun See the ufshcd-pltfrm.txt for details. 18*4882a593Smuzhiyun- clocks : List of phandle and clock specifier pairs. 19*4882a593Smuzhiyun- clock-names : List of clock input name strings sorted in the same 20*4882a593Smuzhiyun order as the clocks property. "core_clk" is mandatory. 21*4882a593Smuzhiyun Depending on a type of a PHY, 22*4882a593Smuzhiyun the "phy_clk" clock can also be added, if needed. 23*4882a593Smuzhiyun 24*4882a593SmuzhiyunExample: 25*4882a593Smuzhiyun ufs@fd030000 { 26*4882a593Smuzhiyun compatible = "cdns,ufshc", "jedec,ufs-2.0"; 27*4882a593Smuzhiyun reg = <0xfd030000 0x10000>; 28*4882a593Smuzhiyun interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>; 29*4882a593Smuzhiyun freq-table-hz = <0 0>, <0 0>; 30*4882a593Smuzhiyun clocks = <&ufs_core_clk>, <&ufs_phy_clk>; 31*4882a593Smuzhiyun clock-names = "core_clk", "phy_clk"; 32*4882a593Smuzhiyun }; 33