1*4882a593SmuzhiyunTimer64 2*4882a593Smuzhiyun------- 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunThe timer64 node describes C6X event timers. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired properties: 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun- compatible: must be "ti,c64x+timer64" 9*4882a593Smuzhiyun- reg: base address and size of register region 10*4882a593Smuzhiyun- interrupts: interrupt id 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunOptional properties: 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun- ti,dscr-dev-enable: Device ID used to enable timer IP through DSCR interface. 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun- ti,core-mask: on multi-core SoCs, bitmask of cores allowed to use this timer. 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunExample: 19*4882a593Smuzhiyun timer0: timer@25e0000 { 20*4882a593Smuzhiyun compatible = "ti,c64x+timer64"; 21*4882a593Smuzhiyun ti,core-mask = < 0x01 >; 22*4882a593Smuzhiyun reg = <0x25e0000 0x40>; 23*4882a593Smuzhiyun interrupt-parent = <&megamod_pic>; 24*4882a593Smuzhiyun interrupts = < 16 >; 25*4882a593Smuzhiyun }; 26