1*4882a593Smuzhiyun* Renesas R-Mobile/R-Car Timer Unit (TMU) 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe TMU is a 32-bit timer/counter with configurable clock inputs and 4*4882a593Smuzhiyunprogrammable compare match. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunChannels share hardware resources but their counter and compare match value 7*4882a593Smuzhiyunare independent. The TMU hardware supports up to three channels. 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunRequired Properties: 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun - compatible: must contain one or more of the following: 12*4882a593Smuzhiyun - "renesas,tmu-r8a7740" for the r8a7740 TMU 13*4882a593Smuzhiyun - "renesas,tmu-r8a774a1" for the r8a774A1 TMU 14*4882a593Smuzhiyun - "renesas,tmu-r8a774b1" for the r8a774B1 TMU 15*4882a593Smuzhiyun - "renesas,tmu-r8a774c0" for the r8a774C0 TMU 16*4882a593Smuzhiyun - "renesas,tmu-r8a7778" for the r8a7778 TMU 17*4882a593Smuzhiyun - "renesas,tmu-r8a7779" for the r8a7779 TMU 18*4882a593Smuzhiyun - "renesas,tmu-r8a77970" for the r8a77970 TMU 19*4882a593Smuzhiyun - "renesas,tmu-r8a77980" for the r8a77980 TMU 20*4882a593Smuzhiyun - "renesas,tmu" for any TMU. 21*4882a593Smuzhiyun This is a fallback for the above renesas,tmu-* entries 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun - reg: base address and length of the registers block for the timer module. 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun - interrupts: interrupt-specifier for the timer, one per channel. 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun - clocks: a list of phandle + clock-specifier pairs, one for each entry 28*4882a593Smuzhiyun in clock-names. 29*4882a593Smuzhiyun - clock-names: must contain "fck" for the functional clock. 30*4882a593Smuzhiyun 31*4882a593SmuzhiyunOptional Properties: 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun - #renesas,channels: number of channels implemented by the timer, must be 2 34*4882a593Smuzhiyun or 3 (if not specified the value defaults to 3). 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun 37*4882a593SmuzhiyunExample: R8A7779 (R-Car H1) TMU0 node 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun tmu0: timer@ffd80000 { 40*4882a593Smuzhiyun compatible = "renesas,tmu-r8a7779", "renesas,tmu"; 41*4882a593Smuzhiyun reg = <0xffd80000 0x30>; 42*4882a593Smuzhiyun interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>, 43*4882a593Smuzhiyun <0 33 IRQ_TYPE_LEVEL_HIGH>, 44*4882a593Smuzhiyun <0 34 IRQ_TYPE_LEVEL_HIGH>; 45*4882a593Smuzhiyun clocks = <&mstp0_clks R8A7779_CLK_TMU0>; 46*4882a593Smuzhiyun clock-names = "fck"; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #renesas,channels = <3>; 49*4882a593Smuzhiyun }; 50