1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/timer/renesas,ostm.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Renesas OS Timer (OSTM) 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Chris Brandt <chris.brandt@renesas.com> 11*4882a593Smuzhiyun - Geert Uytterhoeven <geert+renesas@glider.be> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyundescription: 14*4882a593Smuzhiyun The OSTM is a multi-channel 32-bit timer/counter with fixed clock source that 15*4882a593Smuzhiyun can operate in either interval count down timer or free-running compare match 16*4882a593Smuzhiyun mode. 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun Channels are independent from each other. 19*4882a593Smuzhiyun 20*4882a593Smuzhiyunproperties: 21*4882a593Smuzhiyun compatible: 22*4882a593Smuzhiyun items: 23*4882a593Smuzhiyun - enum: 24*4882a593Smuzhiyun - renesas,r7s72100-ostm # RZ/A1H 25*4882a593Smuzhiyun - renesas,r7s9210-ostm # RZ/A2M 26*4882a593Smuzhiyun - const: renesas,ostm # Generic 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun reg: 29*4882a593Smuzhiyun maxItems: 1 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun interrupts: 32*4882a593Smuzhiyun maxItems: 1 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun clocks: 35*4882a593Smuzhiyun maxItems: 1 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun power-domains: 38*4882a593Smuzhiyun maxItems: 1 39*4882a593Smuzhiyun 40*4882a593Smuzhiyunrequired: 41*4882a593Smuzhiyun - compatible 42*4882a593Smuzhiyun - reg 43*4882a593Smuzhiyun - interrupts 44*4882a593Smuzhiyun - clocks 45*4882a593Smuzhiyun - power-domains 46*4882a593Smuzhiyun 47*4882a593SmuzhiyunadditionalProperties: false 48*4882a593Smuzhiyun 49*4882a593Smuzhiyunexamples: 50*4882a593Smuzhiyun - | 51*4882a593Smuzhiyun #include <dt-bindings/clock/r7s72100-clock.h> 52*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/arm-gic.h> 53*4882a593Smuzhiyun ostm0: timer@fcfec000 { 54*4882a593Smuzhiyun compatible = "renesas,r7s72100-ostm", "renesas,ostm"; 55*4882a593Smuzhiyun reg = <0xfcfec000 0x30>; 56*4882a593Smuzhiyun interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>; 57*4882a593Smuzhiyun clocks = <&mstp5_clks R7S72100_CLK_OSTM0>; 58*4882a593Smuzhiyun power-domains = <&cpg_clocks>; 59*4882a593Smuzhiyun }; 60