1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/timer/nxp,tpm-timer.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: NXP Low Power Timer/Pulse Width Modulation Module (TPM) 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Dong Aisheng <aisheng.dong@nxp.com> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyundescription: | 13*4882a593Smuzhiyun The Timer/PWM Module (TPM) supports input capture, output compare, 14*4882a593Smuzhiyun and the generation of PWM signals to control electric motor and power 15*4882a593Smuzhiyun management applications. The counter, compare and capture registers 16*4882a593Smuzhiyun are clocked by an asynchronous clock that can remain enabled in low 17*4882a593Smuzhiyun power modes. TPM can support global counter bus where one TPM drives 18*4882a593Smuzhiyun the counter bus for the others, provided bit width is the same. 19*4882a593Smuzhiyun 20*4882a593Smuzhiyunproperties: 21*4882a593Smuzhiyun compatible: 22*4882a593Smuzhiyun const: fsl,imx7ulp-tpm 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun reg: 25*4882a593Smuzhiyun maxItems: 1 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun interrupts: 28*4882a593Smuzhiyun maxItems: 1 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun clocks: 31*4882a593Smuzhiyun items: 32*4882a593Smuzhiyun - description: SoC TPM ipg clock 33*4882a593Smuzhiyun - description: SoC TPM per clock 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun clock-names: 36*4882a593Smuzhiyun items: 37*4882a593Smuzhiyun - const: ipg 38*4882a593Smuzhiyun - const: per 39*4882a593Smuzhiyun 40*4882a593Smuzhiyunrequired: 41*4882a593Smuzhiyun - compatible 42*4882a593Smuzhiyun - reg 43*4882a593Smuzhiyun - interrupts 44*4882a593Smuzhiyun - clocks 45*4882a593Smuzhiyun - clock-names 46*4882a593Smuzhiyun 47*4882a593SmuzhiyunadditionalProperties: false 48*4882a593Smuzhiyun 49*4882a593Smuzhiyunexamples: 50*4882a593Smuzhiyun - | 51*4882a593Smuzhiyun #include <dt-bindings/clock/imx7ulp-clock.h> 52*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/arm-gic.h> 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun timer@40260000 { 55*4882a593Smuzhiyun compatible = "fsl,imx7ulp-tpm"; 56*4882a593Smuzhiyun reg = <0x40260000 0x1000>; 57*4882a593Smuzhiyun interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 58*4882a593Smuzhiyun clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, 59*4882a593Smuzhiyun <&pcc2 IMX7ULP_CLK_LPTPM5>; 60*4882a593Smuzhiyun clock-names = "ipg", "per"; 61*4882a593Smuzhiyun }; 62